View 28F128L18_4855706.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

order number: 251902-12 november 2007 numonyx? strataflash wireless memory (l18) 28F128L18, 28f256l18 datasheet product features ? high performance read-while-write/erase ? 85 ns initial access ? 54 mhz with zero wait state, 14 ns clock-to- data output synchronous-burst mode ? 25 ns asynchronous-page mode ? 4-, 8-, 16-, and continuous-word burst mode ? burst suspend ? programmable wait configuration ? buffered enhanced factory programming (befp) at 5 s/byte (typ) ? 1.8 v low-power buffered programming at 7 s/byte (typ) ? architecture ? asymmetrically-blocked architecture ? multiple 8-mbit partitions: 128-mbit devices ? multiple 16-mbit partitions: 256-mbit devices ? four 16-kword parameter blocks: top or bottom configurations ? 64-kword main blocks ? dual-operation: read-while-write (rww) or read-while-erase (rwe) ? status register for partition and device status ? power ?v cc (core) = 1.7 v - 2.0 v ?v ccq (i/o) = 1.35 v - 2.0 v, 1.7 v - 2.0 v ? standby current: 30 a (typ) for 256-mbit ? 4-word synchronous read current: 15 ma (typ) at 54 mhz ?automatic power savings mode ? security ? otp space: 64 unique factory device identifier bits; 64 user-programmable otp bits; additional 2048 user-programmable otp bits ? absolute write protection: v pp = gnd ? power-transition erase/program lockout ? individual zero-latency block locking ? individual block lock-down ? software ? 20 s (typ) program suspend ? 20 s (typ) erase suspend ?numonyx ? flash data integrator optimized ? basic command set (bcs) and extended command set (ecs) compatible ? common flash interface (cfi) capable ? quality and reliability ? expanded temperature: ?25 c to +85 c ? minimum 100,000 erase cycles per block ? intel etox* viii process technology (0.13 m) ? density and packaging ? 128- and 256-mbit density in vf bga packages ? 128/0 and 256/0 density in scsp ? 16-bit wide data bus
datasheet november 2007 2 251902-12 legal lines and disc laim ers information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear f acility applications. numonyx b.v. may make changes to specifications and product descriptions at any time, without notice. numonyx b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights tha t relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implie d, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx, the numonyx logo, and strataflash are trademarks or registered trademarks of numonyx b.v. or its subsidiaries in other countries. *other names and brands may be claimed as the property of others. copyright ? 2007, numonyx b.v., all rights reserved.
november 2007 datasheet 251902-12 3 numonyx? strataflash ? wireless memory (l18) contents 1.0 introduction .............................................................................................................. 8 1.1 nomenclature ..................................................................................................... 8 1.2 acronyms........................................................................................................... 9 1.3 conventions ....................................................................................................... 9 2.0 functional overview ................................................................................................ 10 3.0 package information ............................................................................................... 11 3.1 vf bga packages .............................................................................................. 11 3.2 scsp packages ................................................................................................. 13 4.0 ballout and signal descriptions ............................................................................... 15 4.1 signal ballout ................................................................................................... 15 4.1.1 vf bga package ballout .......................................................................... 15 4.1.2 scsp package ballout ............................................................................. 17 4.2 signal descriptions ............................................................................................ 18 4.2.1 vf bga package signal descriptions ......................................................... 18 4.2.2 128/0 and 256/0 scsp package signal descriptions .................................... 19 4.3 memory map..................................................................................................... 20 5.0 maximum ratings and operating conditions ............................................................ 23 5.1 absolute maximum ratings................................................................................. 23 5.2 operating conditions ......................................................................................... 23 6.0 electrical specifications ........................................................................................... 24 6.1 dc current characteristics.................................................................................. 24 6.2 dc voltage characteristics.................................................................................. 25 7.0 ac characteristics ................................................................................................... 26 7.1 ac test conditions ............................................................................................ 26 7.2 capacitance...................................................................................................... 27 7.3 ac read specifications (vccq = 1.35 v ? 2.0 v) ................................................... 27 7.4 ac read specifications 128-mbit (vccq = 1.7?2.0 v) ............................................ 28 7.5 ac read specifications 256-mbit (vccq = 1.7?2.0 v) ............................................ 30 7.6 ac write specifications ...................................................................................... 35 7.7 program and erase characteristics....................................................................... 38 8.0 power and reset specifications ............................................................................... 40 8.1 power up and down .......................................................................................... 40 8.2 reset............................................................................................................... 40 8.3 power supply decoupling ................................................................................... 41 8.4 automatic power saving..................................................................................... 41 9.0 device operations ................................................................................................... 42 9.1 bus operations ................................................................................................. 42 9.1.1 reads ................................................................................................... 42 9.1.2 writes................................................................................................... 43 9.1.3 output disable ....................................................................................... 43 9.1.4 standby ................................................................................................ 43 9.1.5 reset.................................................................................................... 43 9.2 device commands............................................................................................. 44 9.3 command definitions......................................................................................... 45 10.0 read operations ...................................................................................................... 48 10.1 asynchronous page-mode read ........................................................................... 48 10.2 synchronous burst-mode read............................................................................ 48
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 4 251902-12 10.2.1 burst suspend........................................................................................49 10.3 read configuration register (rcr) .......................................................................49 10.3.1 read mode.............................................................................................50 10.3.2 latency count ........................................................................................50 10.3.3 wait polarity .........................................................................................52 10.3.3.1 wait signal function.................................................................52 10.3.4 data hold ..............................................................................................53 10.3.5 wait delay............................................................................................54 10.3.6 burst sequence ......................................................................................54 10.3.7 clock edge.............................................................................................55 10.3.8 burst wrap ............................................................................................55 10.3.9 burst length ..........................................................................................55 11.0 programming operations .........................................................................................56 11.1 word programming ............................................................................................56 11.1.1 factory word programming......................................................................57 11.2 buffered programming .......................................................................................57 11.3 buffered enhanced factory programming ..............................................................58 11.3.1 buffered efp requirements and considerations...........................................58 11.3.2 buffered efp setup phase ........................................................................59 11.3.3 buffered efp program/verify phase ...........................................................59 11.3.4 buffered efp exit phase ...........................................................................60 11.4 program suspend ..............................................................................................60 11.5 program resume ...............................................................................................60 11.6 program protection ............................................................................................61 12.0 erase operations ......................................................................................................62 12.1 block erase .......................................................................................................62 12.2 erase suspend ..................................................................................................62 12.3 erase resume ...................................................................................................63 12.4 erase protection ................................................................................................63 13.0 security modes ........................................................................................................64 13.1 block locking ....................................................................................................64 13.1.1 lock block .............................................................................................64 13.1.2 unlock block ..........................................................................................64 13.1.3 lock-down block ....................................................................................64 13.1.4 block lock status ...................................................................................65 13.1.5 block locking during suspend ..................................................................65 13.2 protection registers ...........................................................................................66 13.2.1 reading the protection registers...............................................................67 13.2.2 programming the protection registers .......................................................68 13.2.3 locking the protection registers ...............................................................68 14.0 dual-operation considerations ................................................................................69 14.1 memory partitioning ...........................................................................................69 14.2 read-while-write command sequences................................................................69 14.2.1 simultaneous operation details ................................................................70 14.2.2 synchronous and asynchronous rww characteristics and waveforms ...........70 14.2.2.1 write operation to asynchronous read transition ............................70 14.2.2.2 write to synchronous read operation transition..............................70 14.2.2.3 write operation with clock active ................................................71 14.2.3 read operation during buffered programming ............................................71 14.3 simultaneous operation restrictions ....................................................................72 15.0 special read states ..................................................................................................73 15.1 read status register..........................................................................................73
november 2007 datasheet 251902-12 5 numonyx? strataflash ? wireless memory (l18) 15.1.1 clear status register .............................................................................. 74 15.2 read device identifier........................................................................................ 74 15.3 cfi query ........................................................................................................ 75 appendix a write state machine (wsm) .......................................................................... 76 appendix b flowcharts .................................................................................................... 83 appendix c common flash interface ............................................................................... 91 appendix d additional information ............................................................................... 101 appendix e ordering information .................................................................................. 102
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 6 251902-12 revision history revision date revision description 10/15/02 -001 initial release 01/20/03 -002 revised 256-mbit partition size revised 256-mbit memory map change wait function to de-assert during asynchronous operations (asynchronous reads and all writes) change wait function to active during synchronous non-array read updated all waveforms to reflect new wait function revised section 8.2.2 added synchronous read to write transition section improved 1.8 volt i/o bin 2 speed to 95ns from 105ns added new ac specs: r15, r16, r17, r111, r311, r312, w21, and w22 various text edits 04/11/03 -003 added scsp for 128/0 and 256/0 ball-out and mechanical drawing 08/04/03 -004 changed i ccs and i ccr values added 256-mbit ac speed changed program and erase spec combined the buffered programming flow chart and read while buffered programming flow chart revised read while buffered programming flow chart revised appendix a write state machine revised cfi table 21 cfi identification various text edits. 01/20/04 -005 various text clarifications, various text edits, block locking state diagram clarification, synchronous read to write timing clarification, write to synchronous read timing clarification 05/22/04 -006 minor text edits changed capacitance values changed standby current (typ), power down current (typ), erase suspend current (typ), and automatic power savings current (typ) updated transient equialent testing load circuit 09/02/04 -007 added table 19, ?bus operations summary? on page 42 added the following order items: * rd48f2000l0ytq0, rd48f2000l0ybq0 * rd48f4000l0ytq0, rd48f4000l0ybq0 * pf48f3000l0ytq0, pf48f3000l0ybq0 * pf48f4000l0ytq0, pf48f4000l0ybq0 * nz48f4000l0ytq0, nz48f4000l0ybq0 * jz48f4000loytq0, jz48f4000loybq0 09/29/04 -008 removed two mechanical drawings for 9x7.7x1.0 mm and 9x11x1.0 mm added mechanical drawing figure 4, ?256-mbit, 88-ball (80-active ball) drawing and dimensions (8x11x1.0 mm)? on page 14 corrected 256l18 package size from 8x10x1.2 mm to 8x11x1.2 mm in the order information table. 04/22/05 -009 removed bin 2 lc and frequency support tables added back vf bga mechanical drawings renamed 256-mbit ut-scsp to be 256-mbit scsp updated ordering info minor text edits converted datasheet to new template in table 5, ?bottom parameter memory map, 128-mbit? on page 22 , corrected 256-mbit blk 131 address range from 100000 - 10ffff to 800000 - 80ffff in section 5.1, ?absolute maximum ratings? on page 23 , corrected voltage on any signal (except vcc, vpp) from -0.5 v to +3.8 v to -0.5 v to +2.5 v in section e.2, ?ordering information for scsp? on page 105 , corrected package designators for leaded and lead-free packages from rd/pf to nz/jz
november 2007 datasheet 251902-12 7 numonyx? strataflash ? wireless memory (l18) 8/4/05 -010 recreated the pdf to resolve some display problems. 2/13/06 -011 removed 64-mbit density various text edits november 2007 12 applied numonyx branding.
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 8 251902-12 1.0 introduction this document provides information about the numonyx? strataflash ? wireless memory device (l18). this document describes the device features, operation, and specifications. the numonyx strataflash ? wireless memory (l18) device is the latest generation of numonyx strataflash ? memory devices featuring flexible, multiple-partition, dual operation. it provides high performance synchronous-burst read mode and asynchronous read mode using 1.8 v low-voltage, multi-level cell (mlc) technology. the multiple-partition architecture enables background programming or erasing to occur in one partition while code execution or data reads take place in another partition. this dual-operation architecture also allows a system to interleave code operations while program and erase operations take place in the background. the 8- mbit or 16-mbit partitions allow system designers to choose the size of the code and data segments. the l18 wireless memory device is manufactured using intel 0.13 m etox* viii process technology. it is available in industry-standard chip scale packaging. 1.1 nomenclature 1.8 v: range of 1.7 v ? 2.0 v (except where noted) 1.8 v extended range: range of 1.35 v ? 2.0 v vpp = 9.0 v: v pp voltage range of 8.5 v ? 9.5 v block: a group of bits, bytes or words within the flash memory array that erase simultaneously when the erase command is issued to the device. the numonyx? strataflash ? wireless memory (l18) has two block sizes: 16-kword, and 64-kword. main block: an array block that is usually used to store code and/or data. main blocks are larger than parameter blocks. parameter block: an array block that is usually used to store frequently changing data or small system parameters that traditionally would be stored in eeprom. top parameter device: previously referred to as a top-boot device, a device with its parameter partition located at the highest physical address of its memory map. parameter blocks within a parameter partition are located at the highest physical address of the parameter partition. bottom parameter device: previously referred to as a bottom-boot device, a device with its parameter partition located at the lowest physical address of its memory map. parameter blocks within a parameter partition are located at the lowest physical address of the parameter partition. partition: a group of blocks that share common program/erase circuitry. blocks within a partition also share a common status register. if any block within a partition is being programmed or erased, only status register data (rather than array data) is available when any address within that partition is read. main partition: a partition containing only main blocks. parameter partition: a partition containing parameter blocks and main blocks.
november 2007 datasheet 251902-12 9 numonyx? strataflash ? wireless memory (l18) 1.2 acronyms cui: command user interface mlc: multi-level cell otp: one-time programmable plr: protection lock register pr: protection register rcr: read configuration register rfu: reserved for future use sr: status register wsm: write state machine 1.3 conventions vcc: signal or voltage connection v cc : signal or voltage level 0x: hexadecimal number prefix 0b: binary number prefix sr[4]: denotes an individual register bit. a[15:0]: denotes a group of similarly named signals, such as address or data bus. a5: denotes one element of a signal group membership, such as an address. bit: binary unit byte: eight bits word: two bytes, or sixteen bits kbit: 1024 bits kbyte: 1024 bytes kword: 1024 words mbit: 1,048,576 bits mbyte: 1,048,576 bytes mword: 1,048,576 words
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 10 251902-12 2.0 functional overview the numonyx? strataflash ? wireless memory (l18) provides read-while-write and read-while-erase capability with density upgrades through 256-mbit. this family of devices provides high performance at low voltage on a 16-bit data bus. individually erasable memory blocks are sized for optimum code and data storage. each device density contains one parameter partition and several main partitions. the flash memory array is grouped into multiple 8-mbit or 16-mbit partitions. by dividing the flash memory into partitions, program or erase operations can take place at the same time as read operations. although each partition has write, erase, and burst read capabilities, simultaneous operation is limited to write or erase in one partition while other partitions are in read mode. the numonyx? strataflash ? wireless memory (l18) allows burst reads that cross partition boundaries. user application code is responsible for ensuring that burst reads do not cross into a partition that is programming or erasing. upon initial power up or return from reset, the device defaults to asynchronous page- mode read. configuring the read configuration register enables synchronous burst- mode reads. in synchronous burst mode, output data is synchronized with a user- supplied clock signal. a wait signal provides easy cpu-to-flash memory synchronization. in addition to the enhanced architecture and interface, the numonyx? strataflash ? wireless memory (l18) incorporates technolo gy that enables fast factory program and erase operations. designed for low-volt age systems, the numonyx? strataflash ? wireless memory (l18) supports read operations with v cc at 1.8 volt, and erase and program operations with v pp at 1.8 v or 9.0 v. buffered enhanced factory programming (buffered efp) provides the fastest flash array programming performance with v pp at 9.0 volt, which increases factory throughput. with v pp at 1.8 v, vcc and vpp can be tied together for a simple, ultra-low power design. in addition to voltage flexibility, a dedicated v pp connection provides complete data protection when v pp is less than v pplk . a command user interface (cui) is the interface between the system processor and all internal operations of the numonyx? strataflash ? wireless memory (l18). an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase and program. a status register indicates erase or program completion and any errors that may have occurred. an industry-standard command sequence invokes program and erase automation. each erase operation erases one block. the erase suspend feature allows system software to pause an erase cycle to read or program data in another block. program suspend allows system software to pause programming to read other locations. data is programmed in word increments. the numonyx? strataflash ? wireless memory (l18) offers power savings through automatic power savings (aps) mode and standby mode. the device automatically enters aps following read-cycle completion. standby is initiated when the system deselects the device by deasserting ce# or by asserting rst#. combined, these features can significantly reduce power consumption. the numonyx? strataflash ? wireless memory (l18)?s protection register allows unique flash device identification that can be used to increase system security. also, the individual block lock feature provides zero-latency block locking and unlocking.
november 2007 datasheet 251902-12 11 numonyx? strataflash ? wireless memory (l18) 3.0 package information 3.1 vf bga packages figure 1: 128-mbit, 56-ball vf bga package drawing and dimensions e seating plane top view - ball side down bottom view - ball side up y a a1 d a2 a1 index mark s1 s2 e b a1 index mark a b c d e f g 8 7 6 5 4 3 2 1 876 54321 a b c d e f g note: drawing not to scale side view millimeters inches dimensions symbol min nom max notes min nom max package height a 1.000 0.0394 ball height a1 0.150 0.0059 package body thickness a2 0.665 0.0262 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body length (128mb) d 7.600 7.700 7.800 0.2992 0.3031 0.3071 package body width (128mb) e 8.900 9.000 9.100 0.3504 0.3543 0.3583 pitch e 0.750 0.0295 ball (lead) count n 56 56 seating plane coplanarity y 0.100 0.0039 corner to ball a1 distance along d s1 1.125 1.225 1.325 0.0443 0.0482 0.0522 corner to ball a1 distance along e s2 2.150 2.250 2.350 0.0846 0.0886 0.0925
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 12 251902-12 figure 2: 256-mbit, 79-ball vf bga package drawing and dimensions dimensions table side view top view - ball side down bottom view - ball side up a2 a seating plane y a1 s2 a1 index mark e b a1 index mark s1 e d a b c d e f g 4 5 6 7321 8 9 10 11 12 13 a b c d e f g 4567 3 2 189 10 11 1213 drawing not to scale millimeters inches dimens ions s ymbol min nom max notes min nom max package height a 1.000 0.0394 ball heig ht a1 0.150 0.0059 package bo dy thicknes s a2 0.665 0.0262 ball (lead) w id th b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package bo dy leng th (256mb) d 10.900 11.000 11.100 0.4291 0.4331 0.4370 package bo dy w id th (256mb) e 8.900 9.000 9.100 0.3504 0.3543 0.3583 pitch e 0.750 0.0295 ball (lead) count n 79 79 seating plane coplanarity y 0.100 0.0039 corn er to ball a 1 dis tance alo ng d s1 0.900 1.000 1.100 0.0354 0.0394 0.0433 corner to ball a1 distance along e s2 2.150 2.250 2.350 0.0846 0.0886 0.0925
november 2007 datasheet 251902-12 13 numonyx? strataflash ? wireless memory (l18) 3.2 scsp packages figure 3: 128-mbit, 88-ball (80-active ball) scsp drawing and dimensions (8x10x1.2 mm) millimete rs inches dimens ions s ymbol mi n n om max notes m in n om m ax pa ckag e h eig h t a 1.200 0.0472 ball h eig h t a 1 0.200 0.0079 pa ckag e b o d y t h ick ne s s a 2 0.860 0.03 39 ball (lead ) w id th b 0.325 0.375 0.425 0.0128 0.01 48 0.0167 pa ckag e b o d y len g th d 9.900 10.000 10.1 00 0.3898 0.39 37 0.3976 pa ckag e b o d y w id th e 7.900 8.000 8.100 0.3110 0.31 50 0.3189 pitch e 0.800 0.03 15 ba ll (le a d ) c o u n t n 88 88 se atin g plan e c o plan arity y 0.100 0.0039 co rne r t o b all a 1 dis tan ce a lo n g e s1 1.100 1.200 1.300 0.0433 0.04 72 0.0512 co rne r t o b all a 1 dis tan ce a lo n g d s2 0.500 0.600 0.700 0.0197 0.02 36 0.0276 top view - ball d own bottom view - ball up a a2 d e y a1 draw ing not to scale. s2 s1 a c b e d g f j h k l m e 1 2 3 4 5 6 7 8 b a c b e d g f j h k l m a1 index mark 12 345 678
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 14 251902-12 figure 4: 256-mbit, 88-ball (80-active ball) drawing and dimensions (8x11x1.0 mm) m illim eters in ches d im ensions s ym bol m in n om m ax n otes m in n om m ax package h eight a 1.00 0.0394 ball h eig h t a 1 0.117 0.0046 packag e body t h icknes s a 2 0.740 0.0291 ball (lead ) w id th b 0.300 0.350 0.400 0.0118 0.0138 0.0157 packag e body len gth d 10.900 11.00 11.100 0.4291 0.4331 0.4370 packag e body w id th e 7.900 8.00 8.100 0.3110 0.3150 0.3189 p itc h e 0.8 0 0 .0 31 5 ball (lead) count n 88 88 seatin g plan e cop lanarity y 0.100 0.0039 corner to ball a 1 distance a lon g e s1 1.100 1.200 1.300 0.0433 0.0472 0.0512 t op view - ball d ow n bottom view - ball u p a a2 d e y a1 d rawing not to scale. s2 s1 a c b e d g f j h k l m e 1 2 3 4 5 6 7 8 b a c b e d g f j h k l m a1 index mark 123 456 78 note: dim ensions a1, a2, and b are preliminary
november 2007 datasheet 251902-12 15 numonyx? strataflash ? wireless memory (l18) 4.0 ballout and signal descriptions 4.1 signal ballout this section includes signal ballouts for the following packages: ?vf bga package ballout ?scsp package ballout 4.1.1 vf bga package ballout the numonyx? strataflash ? wireless memory (l18) is available in a vf bga package with 0.75 mm ball-pitch. figure 5 shows the ballout for the 128-mbit device in the 56- ball vf bga package with a 7x8 active-ball matrix. figure 6 shows the device ballout for the 256-mbit device in the 63-ball vf bga package with a 7x9 active-ball matrix. both package densities are ideal for space-constrained board applications figure 5: 7x8 active-ball matrix for 128-mbit density in vf bga packages vfbga 7x8 bottom vi ew - bal l side up vfbga 7x8 top vi ew - bal l si de down 23 456 7 8 1 a8 vss vcc vpp a18 a6 a4 a9 a20 clk rst# a17 a5 a3 a10 a21 w e# a19 a7 a2 a14 w ait a16 d12 wp# a22 d15 d6 d4 d2 d1 ce# a0 d14 d13 d11 d10 d9 d0 oe# adv# a1 vssq vcc d3 vccq d8 vssq a11 a12 a13 a15 vccq vss d7 d5 a b c d e f g 2 3 4 5 6 7 81 a8 vss vcc vpp a18 a6 a4 a9 a20 clk rst# a17 a5 a3 a10 a21 we# a19 a7 a2 a14 wait a16 d12 wp# a22 d15 d6 d4 d2 d1 ce# a0 d14 d13 d11 d10 d9 d0 oe# adv# a1 vssq vcc d3 vccq d8 vssq a11 a12 a13 a15 vccq vss d7 d5 a b c d e f g y
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 16 251902-12 note: on lower density devices upper address balls can be treated as rfus. (a24 is for 512-mbit and a25 is for 1-gbit densities). all ball locations are populated. figure 6: 7x9 active-ball matrix for 256-mbit density in vf bga package rfu vcc a4 a6 a18 vpp vss a8 a11 rfu clk a3 a5 a17 rst# a20 a9 a12 a25 adv# a2 a7 a19 we# a21 a10 a13 a24 a16 a1 a22 wp# d12 wait a14 a15 a23 d4 a0ce#d1d2 d6d15vccq rfu d11 oe# d0 d9 d10 d13 d14 vss rfu vcc vssq d8 vccq d3 d5 vssq d7 bottom view - ball side up a b c d e f g du du du du du du du du du du du du du du du du 11 10 12 13 7 5 4 3 2 1 8 96 rfu vcc a4 a6 a18 vpp vss a8 a11 rfu clk a3 a5 a17 rst# a20 a9 a12 a25 adv# a2 a7 a19 we # a21 a10 a13 a24 a16 a1 a22 wp # d12 wa i t a14 a15 a23 d4 a0 ce# d1 d2 d6 d15 vccq rfu d11 oe# d0 d9 d10 d13 d14 vss rfu vcc vssq d8 vccq d3 d5 vssq d7 top v iew - ball side down a b c d e f g du du du du du du du du du du du du du du du du 11 10 12 13 7 5 4 3 2 1 89 6
november 2007 datasheet 251902-12 17 numonyx? strataflash ? wireless memory (l18) 4.1.2 scsp package ballout the l18 wireless memory in quad+ ballout device is available in an 88-ball (80-active ball) stacked chip scale package (scsp) for the 128- and 256-mbit devices. for mechanical information, refer to section 3.0, ?package information? on page 11 . figure 7: 88-ball (80-active ball) scsp package ballout f lash s p ecific sr am /psr am specific g lobal legend: top view - ball side dow n 8 7 6 5 4 3 2 1 a b c d e f g h j k l m du a4 du du d u du du du du a5 a3 a2 a 7 a1 a 6 a0 a18 a19 vss vss a23 a24 a25 a17 f2-v c c clk a21 a22 a12 a11 a13 a9 p1-cs# f-vpp, f-vpen a20 a10 a15 f-w e # a 8 d8 d2 d10 d5 d13 w ait a14 a16 f1 -c e # p -m ode vss vss vss p2-cs# f1-v c c f2-vcc vccq f3 -c e # d0 d1 d9 d3 d4 d 6 d7 d15 d11 d12 d 14 f1-o e # f2-o e # p-vcc s-cs2 r-w e# r-ub# r-lb # r-o e# s-v cc s-cs 1# f1-v c c f-w p # a d v # f-r s t# f2-c e # vccq vs s vs s vccq vss
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 18 251902-12 4.2 signal descriptions this section includes signal descriptions for the following packages: ? vf bga package signal descriptions ? scsp package signal descriptions 4.2.1 vf bga package signal descriptions ta b l e 1 describes the active signals used on the numonyx? strataflash ? wireless memory (l18), vf bga package. table 1: signal descriptions (sheet 1 of 2) symbol type name and function a[max:0] input address: device address inputs. 128-mbit: a[22:0]; 256-mbit: a[23:0]. dq[15:0] input/ output data input/outputs: inputs data and commands during write cycles; outputs data during memory, status register, protection register, and read configuration register reads. data balls float when the ce# or oe# are deasserted. data is internally latched during writes. adv# input address valid: active-low input. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first. in asynchronous mode, the address is latched when adv# going high or continuously flows through if adv# is held low. ce# input chip enable: active-low input. ce#-low selects the device. ce#-high deselects the device, placing it in standby, with dq[15:0] and wait in high-z. clk input clock: synchronizes the device with the system?s bus frequency in synchronous-read mode and increments the internal address generator. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first. oe# input output enable: active-low input. oe#-low enables the device?s output data buffers during read cycles. oe#-high places the data outputs in high-z and wait in high-z. rst# input reset: active-low input. rst# resets internal automation and inhibits write operations. this provides data protection during power transitions. rst#-high enables normal operation. exit from reset places the device in asynchronous read array mode. wait output wait: indicates data valid in synchronous array or non-array burst reads. configuration register bit 10 (rcr[10], wt) determines its polarity when asserted. with ce# and oe# at v il , wait?s active output is v ol or v oh when ce# and oe# are asserted. wait is high-z if ce# or oe# is v ih . ? in synchronous array or non-array read modes, wait indicates invalid data when asserted and valid data when deasserted. ? during asynchronous reads, wait is deasserted. ? during writes (when oe# is deasserted), wait is tristated. we# input write enable: active-low input. we# controls writes to the device. address and data are latched on the rising edge of we#. wp# input write protect: active-low input. wp#-low enables the lock-down mechanism. blocks in lock-down cannot be unlocked with the unlock command. wp#-high overrides the lock-down function enabling blocks to be erased or programmed using software commands. vpp power/ lnput erase and program power: a valid voltage on this pin allows erasing or programming. memory contents cannot be altered when v pp v pplk . block erase and program at invalid v pp voltages should not be attempted. set v pp = v cc for in-system program and erase operations. to accommodate resistor or diode drops from the system supply, the v ih level of v pp can be as low as v ppl min. v pp must remain above v ppl min to perform in-system program or erase. vpp may be 0 v during read operations. v pph can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. vpp can be connected tov pph for a cumulative total not to exceed 80 hours. extended use of this pin at v pph may derate flash performance/behavior. vcc power device core power supply: core (logic) source voltage. writes to the flash array are inhibited when v cc v lko . operations at invalid v cc voltages should not be attempted. vccq power output power supply: output-driver source voltage. this ball can be tied directly to v cc if operating within v cc range.
november 2007 datasheet 251902-12 19 numonyx? strataflash ? wireless memory (l18) 4.2.2 128/0 and 256/0 scsp package signal descriptions ta b l e 2 describes the active signals used on the 128/0 and 256/0 scsp. vss power ground: ground reference for device logic voltages. connect to system ground. vssq power ground: ground reference for device output voltages. connect to system ground. du ? do not use: do not use this ball. this ball should not be connected to any power supplies, signals or other balls, and must be left floating. rfu ? reserved for future use: reserved by numonyx for future device functionality and enhancement. table 1: signal descriptions (sheet 2 of 2) symbol type name and function table 2: device signal descriptions for scsp (sheet 1 of 2) symbol type description a[max:0] input address inputs: inputs for all die addresses during read and write operations. ? 128-mbit die: a[max] = a22 ? 256-mbit die: a[max] = a23 dq[15:0] input/ output data inputs/outputs: inputs data and commands during write cycles, outputs data during read cycles. data signals float when the device or its outputs are deselected. data is internally latched during writes. f1-ce# f2-ce# f3-ce# input flash chip enable: low-true: selects the associated flash memory die. when asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. when deasserted, the associated flash die is deselected, power is reduced to standby levels, data and wait outputs are placed in high-z state. f1-ce# selects the flash die. f2-ce# and f3-ce# are available on stacked combinations with two or three flash dies else they are rfu. they each can be tied high to vccq through a 10k-ohm resistor for future design flexibility. s-cs1# s-cs2 input sram chip selects: when both sram chip selects are asserted, sram internal control logic, input buffers, decoders, and sense amplifiers are active. when either/both sram chip selects are deasserted (s-cs1# = v ih or s-cs2 = v il ), the sram is deselected and its power is reduced to standby levels. treat this signal as nc (no connect) for this device. p-cs# input psram chip select: low-true; when asserted, psram internal control logic, input buffers, decoders, and sense amplifiers are active. when deasserted, the psram is deselected and its power is reduced to standby levels. treat this signal as nc (no connect) for this device. f1-oe# f2-oe# input flash output enable: low-true; enables the flash output buffers. oe#-high disables the flash output buffers, and places the flash outputs in high-z. f1-oe# controls the outputs of the flash die. f2-oe# is available on stacked combinations with two or three flash dies else it is rfu. it can be pulled high to vccq through a 10k-ohm resistor for future design flexibility. r-oe# input ram output enable: low-true; r-oe#-low enables the selected ram output buffers. r-oe#-high disables the ram output buffers, and places the selected ram outputs in high-z. treat this signal as nc (no connect) for this device. we# input flash write enable: low-true; we# controls writes to the selected flash die. address and data are latched on the rising edge of we#. r-we# input ram write enable: low-true; r-we# controls writes to the selected ram die. treat this signal as nc (no connect) for this device. clk input flash clock: synchronizes the device with the system?s bus frequency in synchronous-read mode and increments the internal address generator. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first.
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 20 251902-12 4.3 memory map see ta b l e 3 and ta b l e 5 . the memory array is divided into multiple partitions; one parameter partition and several main partitions: ? 128-mbit device. this contains sixteen partitions: one 8-mbit parameter partition, fifteen 8-mbit main partitions. wait output flash wait: indicates data valid in synchronous array or non-array burst reads. configuration register bit 10 (rcr[10], wt) determines its polarity when asserted. with ce# and oe# at v il , wait?s active output is v ol or v oh when ce# and oe# are asserted. wait is high-z if ce# or oe# is v ih . ? in synchronous array or non-array read modes, wait indicates invalid data when asserted and valid data when deasserted. ? in asynchronous page mode, and all write modes, wait is deasserted. wp# input flash write protect: low-true; wp# enables/disables the lock-down protection mechanism of the selected flash die. wp#-low enables the lock-down mechanism - locked down blocks cannot be unlocked with software commands. wp#-high disables the lock-down mechanism, allowing locked down blocks to be unlocked with software commands. adv# input flash address valid: active-low input. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first. in asynchronous mode, the address is latched when adv# going high or continuously flows through if adv# is held low. r-ub# r-lb# input ram upper / lower byte enables: low-true; during ram reads, r-ub#-low enables the ram high order bytes on dq[15:8], and r-lb#-low enables the ram low-order bytes on dq[7:0]. treat this signal as nc (no connect) for this device. rst# input flash reset: low-true; rst#-low initializes flash internal circuitry and disables flash operations. rst#-high enables flash operation. exit from reset places the flash in asynchronous read array mode. p-mode input psram mode: low-true; p-mode is used to program the configuration register, and enter/exit low power mode. treat this signal as nc (no connect) for this device. vpp, vpen power/ input flash program/erase power: a valid voltage on this pin allows erasing or programming. memory contents cannot be altered when v pp v pplk . block erase and program at invalid v pp voltages should not be attempted. set v pp = v cc for in-system program and erase operations. to accommodate resistor or diode drops from the system supply, the v ih level of v pp can be as low as v ppl min. v pp must remain above v ppl min to perform in-system flash modification. vpp may be 0 v during read operations. v pph can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. vpp can be connected to 9 v for a cumulative total not to exceed 80 hours. extended use of this pin at 9 v may reduce block cycling capability. vpen (erase/program/block lock enables) is not available for l18 products. f1-vcc f2-vcc power flash logic power: f1-vcc supplies power to the core logic of flash die #1; f2-vcc supplies power to the core logic of flash die #2. write operations are inhibited when v cc v lko . device operations at invalid v cc voltages should not be attempted. s-vcc power sram power supply: supplies power for sram operations. treat this signal as nc (no connect) for this device. p-vcc power psram power supply: supplies power for psram operations. treat this signal as nc (no connect) for this device. vccq power flash i/o power: supply power for the input and output buffers. vss power ground: connect to system ground. do not float any vss connection. rfu ? reserved for future use: reserve for future device functionality/ enhancements. contact numonyx regarding their future use. du ? do not use: do not connect to any other signal, or power supply; must be left floating. nc ? no connect: no internal connection; can be driven or floated. table 2: device signal descriptions for scsp (sheet 2 of 2)
november 2007 datasheet 251902-12 21 numonyx? strataflash ? wireless memory (l18) ? 256-mbit device. this contains sixteen partitions: one 16-mbit parameter partition, fifteen 16-mbit main partitions. table 3: top parameter memory map, 128-mbit size (kw) blk 128-mbit 8-mbit parameter partition one partition 16 130 7fc000-7fffff 16 129 7f8000-7fbfff 16 128 7f4000-7f7fff 16 127 7f0000-7f3fff 64 126 7e0000-7effff ? ? ? 64 120 780000-78ffff 8-mbit main partitions fifteen partitions 64 119 770000-77ffff ? 64 0 000000-00ffff table 4: top parameter memory map, , 256-mbit size (kw) blk 256-mbit 16-mbit parameter partition one partition 16 258 ffc000-ffffff 16 257 ff8000-ffbfff 16 256 ff4000-ff7fff 16 255 ff0000-ff3fff 64 254 fe0000-feffff ? ? ? 64 240 f00000-ffffff 16-mbit main partitions seven partitions 64 239 ef0000-efffff ? 64 128 800000-80ffff eight partitions 64 127 7f0000-7fffff ? 64 0 000000-00ffff
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 22 251902-12 table 5: bottom parameter memory map, 128-mbit size (kw) blk 128-mbit 8-mbit main partitions fifteen partitions 64 130 7f0000-7fffff ? ? ? 64 11 080000-08ffff 8-mbit parameter partition one partition 64 10 070000-07ffff ? ? ? 64 4 010000-01ffff 16 3 00c000-00ffff 16 2 008000-00bfff 16 1 004000-007fff 16 0 000000-003fff table 6: bottom parameter memory map, 256-mbit size (kw) blk 256-mbit 16-mbit main partitions eight partitions 64 258 ff0000-ffffff ? ? ? 64 131 800000-80ffff seven partitions 64 130 7f0000-7fffff ? ? ? 64 19 100000-10ffff 16-mbit parameter partition one partition 64 18 0f0000-0fffff ? ? ? 64 4 010000-01ffff 16 3 00c000-00ffff 16 2 008000-00bfff 16 1 004000-007fff 16 0 000000-003fff
november 2007 datasheet 251902-12 23 numonyx? strataflash ? wireless memory (l18) 5.0 maximum ratings and operating conditions 5.1 absolute maximum ratings warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. 5.2 operating conditions warning: operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. table 7: absolute maximum ratings table parameter maximum rating notes temperature under bias ?25 c to +85 c storage temperature ?65 c to +125 c voltage on any signal (except v cc , vpp) ?0.5 v to +2.5 v 1 vpp voltage ?0.2 v to +10 v 1,2,3 vcc voltage ?0.2 v to +2.5 v 1 vccq voltage ?0.2 v to +2.5 v 1 output short circuit current 100 ma 4 notes: 1. voltages shown are specified with respect to v ss . minimum dc voltage is ?0.5 v on input/output signals and ?0.2 v on v cc , v ccq , and v pp . during transitions, this level may undershoot to ?2.0 v for periods < 20 ns. maximum dc voltage on v cc is v cc +0.5 v. during transitions, this level may overshoot to v cc +2.0 v for periods < 20 ns. maximum dc voltage on input/output signals and v ccq is v ccq +0.5 v. during transitions, this level may overshoot to v ccq +2.0 v for periods < 20 ns. 2. maximum dc voltage on v pp may overshoot to +14.0 v for periods < 20 ns. 3. program/erase voltage is typically 1.7 v ? 2.0 v. 9.0 v can be applied for 80 hours maximum total, to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles maximum. 9.0 v program/erase voltage may reduce block cycling capability. 4. output shorted for no more than one second. no more than one output shorted at a time. table 8: operating conditions table symbol parameter min max units notes t c operating temperature ?25 +85 c 1 v cc v cc supply voltage 1.7 2.0 v v ccq i/o supply voltage 1.8 v range 1.7 2.0 1.8 v extended range 1.35 2.0 v ppl v pp voltage supply (logic level) 0.9 2.0 2 v pph factory word programming v pp 8.5 9.5 t pph maximum v pp hours v pp = v pph -80hours block erase cycles main and parameter blocks v pp = v cc 100,000 - cycles main blocks v pp = v pph - 1000 parameter blocks v pp = v pph - 2500 notes: 1. t c = case temperature 2. in typical operation, the vpp program voltage is v ppl . vpp can be connected to 8.5 v ? 9.5 v for 1000 cycles on main blocks and 2500 cycles on parameter blocks.
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 24 251902-12 6.0 electrical specifications 6.1 dc current characteristics table 9: dc current specifications (sheet 1 of 2) sym parameter v ccq 1.7 v ? 2.0 v 1.35 v - 2.0 v unit test conditions notes typ max i li input load current - 1 a v cc = v cc max v ccq = v ccq max v in = v ccq or v ss 1 i lo output leakage current dq[15:0], wait -1a v cc = v cc max v ccq = v ccq max v in = v ccq or v ss i ccs i ccd v cc standby, power down 128-mbit 20 70 a v cc = v cc max v ccq = v ccq max ce# = v ccq rst# = v ccq (for i ccs ) rst# = gnd (for i ccd ) wp# = v ih 1,2 256-mbit 25 110 i ccaps aps 128-mbit 20 70 a v cc = v cc max v ccq = v ccq max ce# = v ssq rst# = v ccq all inputs are at rail to rail (v ccq or v ssq ). 256-mbit 25 110 i ccr average v cc read current asynchronous single-word f = 5mhz (1 clk) 13 15 ma v cc = v cc max ce# = v il oe# = v ih inputs: v il or v ih 1 page-mode read f = 13 mhz (5 clk) 89ma4-word read synchronous burst read f = 40mhz, lc = 3 12 16 ma burst length = 4 14 18 ma burst length = 8 16 20 ma burst length = 16 20 25 ma burst length = continuous synchronous burst read f = 54mhz, lc = 4 15 18 ma burst length = 4 18 22 ma burst length = 8 21 25 ma burst length = 16 22 27 ma burst length = continuous i ccw, i cce v cc program current, v cc erase current 35 50 ma v pp = v ppl , program/erase in progress 1,3,4, 7 25 32 ma v pp = v pph , program/erase in progress 1,3,5, 7 i ccws, i cces v cc program suspend current, v cc erase suspend current 128-mbit 20 70 a ce# = v ccq ; suspend in progress 1,6,3 256-mbit 25 110 i pps, i ppws, ippes v pp standby current, v pp program suspend current, v pp erase suspend current 0.2 5 a v pp = v ppl , suspend in progress 1,3
november 2007 datasheet 251902-12 25 numonyx? strataflash ? wireless memory (l18) 6.2 dc voltage characteristics i ppr v pp read 2 15 a v pp v cc 1,3 i ppw v pp program current 0.05 0.10 ma v pp = v ppl, program in progress 822 v pp = v pph, program in progress i ppe v pp erase current 0.05 0.10 ma v pp = v ppl, erase in progress 822 v pp = v pph, erase in progress notes: 1. all currents are rms unless noted. typical values at typical v cc , t c = +25c. 2. i ccs is the average current measured over any 5 ms time interval 5 s after ce# is deasserted. 3. sampled, not 100% tested. 4. v cc read + program current is the sum of v cc read and v cc program currents. 5. v cc read + erase current is the sum of v cc read and v cc erase currents. 6. i cces is specified with the device deselected. if device is read while in erase suspend, current is i cces plus i ccr 7. i ccw , i cce measured over typical or max times specified in section 7.7, ?program and erase characteristics? on page 38 table 9: dc current specifications (sheet 2 of 2) sym parameter v ccq 1.7 v ? 2.0 v 1.35 v - 2.0 v unit test conditions notes typ max table 10: dc voltage specifications sym parameter v ccq 1.35 v ? 2.0 v 1.7 v ? 2.0 v uni t test condition notes min max min max v il input low voltage 00.200.4v 1 v ih input high voltage v ccq ? 0.2 v ccq v ccq ? 0.4 v ccq v1 v ol output low voltage - 0.1 - 0.1 v v cc = v cc min v ccq = v ccq min i ol = 100 a v oh output high voltage v ccq ? 0.1 - v ccq ? 0.1 - v v cc = v cc min v ccq = v ccq min i oh = ?100 a v pplk v pp lock-out voltage - 0.4 - 0.4 v 2 v lko v cc lock voltage 1.0 - 1.0 - v v lkoq v ccq lock voltage 0.9 - 0.9 - v notes: 1. v il can undershoot to ?0.4 v and v ih can overshoot to v ccq + 0.4 v for durations of 20 ns or less. 2. v pp v pplk inhibits erase and program operations. do not use v ppl and v pph outside their valid ranges.
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 26 251902-12 7.0 ac characteristics 7.1 ac test conditions note: ac test inputs are driven at v ccq for logic "1" and 0.0 v for logic "0." input/output timing begins/ends at v ccq /2. input rise and fall times (10% to 90%) < 5 ns. worst case speed occurs at v cc = v cc min. notes: 1. see the following table for component values. 2. test configuration component value for worst case speed conditions. 3. c l includes jig capacitance. figure 8: ac input/output reference waveform input v ccq /2 v ccq /2 output v ccq 0v test points figure 9: transient equivalent testing load circuit device under test out c l table 11: test configuration component value for worst case speed conditions test configuration c l (pf) 1.35 v standard test 30 1.7 v standard test 30 figure 10: clock input ac waveform clk [c] v ih v il r203 r202 r201
november 2007 datasheet 251902-12 27 numonyx? strataflash ? wireless memory (l18) 7.2 capacitance 7.3 ac read specifications (v ccq = 1.35 v ? 2.0 v) table 12: capacitance table symbol parameter signals min typ max unit condition note c in input capacitance address, ce#, we#, oe#, rst#, clk, adv#, wp# 26 7 pf typ temp= 25 c, max temp = 85 c, v cc =v ccq =(0-1.95) v, silicon die 1,2 c out output capacitance data, wait 2 4 5 pf notes: 1. sampled, not 100% tested. 2. silicon die capacitance only, add 1 pf for discrete packages. table 13: ac read specification table, 1.35 v to 2.0 v (sheet 1 of 2) num symbol parameter all densitiesspeed ?90 units notes min max asynchronous specifications r1 t avav read cycle time 90 -ns 6 r2 t avqv address to output valid - 90 ns r3 t elqv ce# low to output valid - 90 ns r4 t glqv oe# low to output valid - 25 ns 1,2 r5 t phqv rst# high to output valid - 150 ns 1 r6 t elqx ce# low to output in low-z 0 - ns 1,3 r7 t glqx oe# low to output in low-z 0 - ns 1,2,3 r8 t ehqz ce# high to output in high-z - 20 ns 1,3 r9 t ghqz oe# high to output in high-z - 20 ns r10 t oh output hold from first occurring address, ce#, or oe# change 0-ns r11 t ehel ce# pulse width high 17 - ns 1 r12 t eltv ce# low to wait valid - 17 ns 1 r13 t ehtz ce# high to wait high z - 17 ns 1,3 r15 t gltv oe# low to wait valid - 17 ns 1 r16 t gltx oe# low to wait in low-z 0 - ns 1,3 r17 t ghtz oe# high to wait in high-z - 20 ns 1,3 latching specifications r101 t avvh address setup to adv# high 7 - ns 1 r102 t elvh ce# low to adv# high 10 - ns r103 t vlqv adv# low to output valid - 90 ns r104 t vlvh adv# pulse width low 7 - ns r105 t vhvl adv# pulse width high 7 - ns r106 t vhax address hold from adv# high 7 - ns 1,4 r108 t apa page address access - 30 ns 1
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 28 251902-12 7.4 ac read specifications 128-mbit (v ccq = 1.7?2.0 v) r111 tphvh rst# high to adv# high 30 - ns 1 clock specifications r200 f clk clk frequency - 47 mhz 1,3 r201 t clk clk period 21.3 - ns r202 t ch/cl clk high/low time 4.5 - ns r203 t fclk/rclk clk fall/rise time - 3 ns synchronous specifications r301 t avch/l address setup to clk 7 - ns 1 r302 t vlch/l adv# low setup to clk 7 - ns r303 t elch/l ce# low setup to clk 7 - ns r304 t chqv / tclqv clk to output valid - 17 ns r305 t chqx output hold from clk 3 - ns 1,5 r306 t chax address hold from clk 7 - ns 1,4,5 r307 t chtv clk to wait valid - 17 ns 1,5 r311 t chvl clk valid to adv# setup 0 - ns 1 r312 t chtx wait hold from clk 3 - ns 1,5 notes: 1. see figure 8, ?ac input/output reference waveform? on page 26 for timing measurements and max allowable input slew rate. 2. oe# may be delayed by up to t elqv ? t glqv after ce#?s falling edge without impact to t elqv. 3. sampled, not 100% tested. 4. address hold in synchronous burst mode is t chax or t vhax , whichever timing specification is satisfied first. 5. applies only to subsequent synchronous reads. 6. the specifications in this table will only be used by customers (1) who desire a 1.35 to 2.0 v ccq operating range or (2) who desire to transition their host controller from a 1.7 v to 2.0 v v ccq voltage now to a lower range in the future. table 13: ac read specification table, 1.35 v to 2.0 v (sheet 2 of 2) num symbol parameter all densitiesspeed ?90 units notes min max table 14: ac read specifications, 128-mbit, 1.7 v to 2.0 v (sheet 1 of 2) num symbol parameter speed ?85 units notes min max asynchronous specifications r1 t avav read cycle time 85 -ns 6 r2 t avqv address to output valid - 85 ns r3 t elqv ce# low to output valid - 85 ns r4 t glqv oe# low to output valid - 20 ns 1,2 r5 t phqv rst# high to output valid - 150 ns 1 r6 t elqx ce# low to output in low-z 0 - ns 1,3 r7 t glqx oe# low to output in low-z 0 - ns 1,2,3 r8 t ehqz ce# high to output in high-z - 17 ns 1,3 r9 t ghqz oe# high to output in high-z - 17 ns r10 t oh output hold from first occurring address, ce#, or oe# change 0 - ns r11 t ehel ce# pulse width high 14 - ns 1
november 2007 datasheet 251902-12 29 numonyx? strataflash ? wireless memory (l18) r12 t eltv ce# low to wait valid - 14 ns 1 r13 t ehtz ce# high to wait high z - 14 ns 1,3 r15 t gltv oe# low to wait valid - 14 ns 1 r16 t gltx oe# low to wait in low-z 0 - ns 1,3 r17 t ghtz oe# high to wait in high-z - 17 ns 1,3 latching specifications r101 t avvh address setup to adv# high 7 - ns 1 r102 t elvh ce# low to adv# high 10 - ns r103 t vlqv adv# low to output valid - 85 ns 1,6 r104 t vlvh adv# pulse width low 7 - ns 1 r105 t vhvl adv# pulse width high 7 - ns r106 t vhax address hold from adv# high 7 - ns 1,4 r108 t apa page address access - 25 ns 1 r111 t phvh rst# high to adv# high 30 - ns 1 clock specifications r200 f clk clk frequency - 54 mhz 1,3 r201 t clk clk period 18.5 - ns r202 t ch/cl clk high/low time 3.5 - ns r203 t fclk/rclk clk fall/rise time - 3 ns synchronous specifications r301 t avch/l address setup to clk 7 - ns 1 r302 t vlch/l adv# low setup to clk 7 - ns r303 t elch/l ce# low setup to clk 7 - ns r304 t chqv / tclqv clk to output valid - 14 ns r305 t chqx output hold from clk 3 - ns 1,5 r306 t chax address hold from clk 7 - ns 1,4,5 r307 t chtv clk to wait valid - 14 ns 1,5 r311 t chvl clk valid to adv# setup 0 - ns 1 r312 t chtx wait hold from clk 3 - ns 1,5 notes: 1. see figure 8, ?ac input/output reference waveform? on page 26 for timing measurements and maximum allowable input slew rate. 2. oe# may be delayed by up to t elqv ? t glqv after ce#?s falling edge without impact to t elqv. 3. sampled, not 100% tested. 4. address hold in synchronous burst mode is t chax or t vhax , whichever timing specification is satisfied first. 5. applies only to subsequent synchronous reads. 6. the specifications in section 7.3 will only be used by customers (1) who desire a 1.35 to 2.0 v ccq operating range or (2) who desire to transition their host controller from a 1.7 v to 2.0 v v ccq voltage now to a lower range in the future. table 14: ac read specifications, 128-mbit, 1.7 v to 2.0 v (sheet 2 of 2) num symbol parameter speed ?85 units notes min max
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 30 251902-12 7.5 ac read specifications 256-mbit (v ccq = 1.7?2.0 v) table 15: ac read specifications, 256-mbit, 1.7 v to 2.0 v (sheet 1 of 2) num symbol parameter speed ?85 units notes min max asynchronous specifications r1 t avav read cycle time v cc = v ccq = 1.8 v ? 2.0 v 85 - ns 6 v cc = v ccq = 1.7 v ? 2.0 v 88 - r2 t avqv address to output valid v cc = v ccq = 1.8 v ? 2.0 v - 85 ns v cc = v ccq = 1.7 v ? 2.0 v - 88 r3 t elqv ce# low to output valid v cc = v ccq = 1.8 v ? 2.0 v - 85 ns v cc = v ccq = 1.7 v ? 2.0 v - 88 r4 t glqv oe# low to output valid - 20 ns 1,2 r5 t phqv rst# high to output valid - 150 ns 1 r6 t elqx ce# low to output in low-z 0 - ns 1,3 r7 t glqx oe# low to output in low-z 0 - ns 1,2,3 r8 t ehqz ce# high to output in high-z - 17 ns 1,3 r9 t ghqz oe# high to output in high-z - 17 ns r10 t oh output hold from first occurring address, ce#, or oe# change 0 - ns r11 t ehel ce# pulse width high 14 - ns 1 r12 t eltv ce# low to wait valid - 14 ns 1 r13 t ehtz ce# high to wait high z - 14 ns 1,3 r15 t gltv oe# low to wait valid - 14 ns 1 r16 t gltx oe# low to wait in low-z 0 - ns 1,3 r17 t ghtz oe# high to wait in high-z - 17 ns 1,3 latching specifications r101 t avvh address setup to adv# high 7 - ns 1 r102 t elvh ce# low to adv# high 10 - ns r103 t vlqv adv# low to output valid v cc = v ccq = 1.8 v ? 2.0 - 85 ns 1,6 v cc = v ccq = 1.7 v ? 2.0 - 88 r104 t vlvh adv# pulse width low 7 - ns 1 r105 t vhvl adv# pulse width high 7 - ns r106 t vhax address hold from adv# high 7 - ns 1,4 r108 t apa page address access - 25 ns 1 r111 t phvh rst# high to adv# high 30 - ns 1 clock specifications r200 f clk clk frequency - 54 mhz 1,3 r201 t clk clk period 18.5 - ns r202 t ch/cl clk high/low time 3.5 - ns r203 t fclk/rclk clk fall/rise time - 3 ns synchronous specifications
november 2007 datasheet 251902-12 31 numonyx? strataflash ? wireless memory (l18) note: wait shown deasserted during asynchronous read mode (rcr[10]=0 wait asserted low). r301 t avch/l address setup to clk 7 - ns 1 r302 t vlch/l adv# low setup to clk 7 - ns r303 t elch/l ce# low setup to clk 7 - ns r304 t chqv / tclqv clk to output valid - 14 ns r305 t chqx output hold from clk 3 - ns 1,5 r306 t chax address hold from clk 7 - ns 1,4,5 r307 t chtv clk to wait valid - 14 ns 1,5 r311 t chvl clk valid to adv# setup 0 - ns 1 r312 t chtx wait hold from clk 3 - ns 1,5 notes: 1. see figure 8, ?ac input/output reference waveform? on page 26 for timing measurements and max allowable input slew rate. 2. oe# may be delayed by up to t elqv ? t glqv after ce#?s falling edge without impact to t elqv. 3. sampled, not 100% tested. 4. address hold in synchronous burst mode is t chax or t vhax , whichever timing specification is satisfied first. 5. applies only to subsequent synchronous reads. 6. the specifications in section 7.3 will only be used by customers (1) who desire a 1.35 to 2.0 v ccq operating range or (2) who desire to transition their host controller from a 1.7 v to 2.0 v v ccq voltage now to a lower range in the future. table 15: ac read specifications, 256-mbit, 1.7 v to 2.0 v (sheet 2 of 2) num symbol parameter speed ?85 units notes min max figure 11: asynchronous single-word read with adv# low r5 r7 r6 r17 r15 r9 r4 r8 r3 r1 r2 r1 a ddress [a] adv# ce# [e} oe# [g] wait [t] data [d/q] rst# [p]
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 32 251902-12 note: wait shown deasserted during asynchronous read mode (rcr[10]=0 wait asserted low). note: wait shown deasserted during asynchronous read mode (rcr[10]=0 wait asserted low). figure 12: asynchronous single-word read with adv# latch r10 r7 r6 r17 r15 r9 r4 r8 r3 r106 r101 r105 r105 r2 r1 a d d re ss [ a ] a[1:0][a] adv# ce# [e} oe# [g] wait [t ] data [d/q] figure 13: asynchronous page-mode read timing r108 r9 r7 r17 r15 r10 r4 r8 r3 r106 r101 r105 r105 r1 r1 r2 a [max:2] [a] a[1:0] adv# ce# [e] oe# [g] wait [t] data [d/q]
november 2007 datasheet 251902-12 33 numonyx? strataflash ? wireless memory (l18) notes: 1. wait is driven per oe# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. 2. this diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by ce# deassertion after the first word in the burst. notes: 1. wait is driven per oe# assertion during synchronous array or non-array read. wait asserted during initial latency and deasserted during valid data (rcr[10] = 0 wait asserted low). 2. at the end of word line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is not 4-word boundary aligned. figure 14: synchronous single-word array or non-array read timing latency count r312 r305 r304 r4 r17 r307 r15 r9 r7 r8 r303 r102 r3 r104 r106 r101 r104 r105 r105 r2 r306 r301 clk [c] a ddress [a] adv# [v] ce# [e] oe# [g] wait [t] data [d/q] figure 15: continuous burst read, showing an output delay timing r305 r305 r305 r305 r304 r4 r7 r312 r307 r15 r303 r102 r3 r106 r105 r105 r101 r2 r304 r304 r304 r306 r302 r301 clk [c] a ddress [a] adv# [v] ce# [e] oe# [g] wait [t] data [d/q]
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 34 251902-12 note: wait is driven per oe# assertion during synchronous array or non-array read. wait asserted during initial latency and deasserted during valid data (rcr[10] = 0 wait asserted low). notes: 1. clk can be stopped in either high or low state. 2. wait is driven per oe# assertion during synchronous array or non-array read. wait asserted during initial latency and deasserted during valid data (rcr[10] = 0 wait asserted low). figure 16: synchronous burst-mode four-word read timing latency count a q0 q1 q2 q3 r307 r10 r304 r305 r3 04 r4 r7 r17 r15 r9 r8 r303 r3 r106 r102 r105 r105 r101 r2 r306 r302 r301 clk [c] a d d re ss [ a ] adv# [v] ce# [e] oe# [g] wait [t] data [d/q] figure 17: burst suspend timing q0 q1 q1 q2 r15 r17 r304 r304 r7 r6 r312 r15 r4 r9 r4 r3 r106 r101 r105 r105 r1 r1 r2 r305 r305 r304 clk address [a] adv# ce# [e] oe# [g] wait [t] we# [w] data [d/q]
november 2007 datasheet 251902-12 35 numonyx? strataflash ? wireless memory (l18) 7.6 ac write specifications table 16: ac write specification table nbr. symbol parameter (1, 2) min max units notes w1 t phwl rst# high recovery to we# low 150 - ns 1,2,3 w2 t elwl ce# setup to we# low 0 - ns 1,2,3 w3 t wlwh we# write pulse width low 50 - ns 1,2,4 w4 t dvwh data setup to we# high 50 - ns 1,2 w5 t avwh address setup to we# high 50 - ns w6 t wheh ce# hold from we# high 0 - ns w7 t whdx data hold from we# high 0 - ns w8 t whax address hold from we# high 0 - ns w9 t whwl we# pulse width high 20 - ns 1,2,5 w10 t vpwh v pp setup to we# high 200 - ns 1,2,3,7 w11 t qvvl v pp hold from status read 0 - ns w12 t qvbl wp# hold from status read 0 - ns 1,2,3,7 w13 t bhwh wp# setup to we# high 200 - ns w14 t whgl we# high to oe# low 0 - ns 1,2,9 w16 t whqv we# high to read valid t avqv + 35 - ns 1,2,3,6,10 write to asynchronous read specifications w18 t whav we# high to address valid 0 - ns 1,2,3,6 write to synchronous read specifications w19 t whch/l we# high to clock valid 19 - ns 1,2,3,6,10 w20 t whvh we# high to adv# high 19 - ns write specifications with clock active w21 t vhwl adv# high to we# low - 20 ns 1,2,3,11 w22 t chwl clock high to we# low - 20 ns notes: 1. write timing characteristics during erase suspend are the same as write-only operations. 2. a write operation can be terminated with either ce# or we#. 3. sampled, not 100% tested. 4. write pulse width low (t wlwh or t eleh ) is defined from ce# or we# low (whichever occurs last) to ce# or we# high (whichever occurs first). hence, t wlwh = t eleh = t wleh = t elwh . 5. write pulse width high (t whwl or t ehel ) is defined from ce# or we# high (whichever occurs first) to ce# or we# low (whichever occurs last). hence, t whwl = t ehel = t whel = t ehwl ). 6. t whvh or t whch/l must be met when transitioning from a write cycle to a synchronous burst read. 7. v pp and wp# should be at a valid level until erase or program success is determined. 8. this specification is only applicable when transitioning from a write cycle to an asynchronous read. see spec w19 and w20 for synchronous read. 9. when doing a read status operation following any command that alters the status register, w14 is 20 ns. 10. add 10ns if the write operations results in a rcr or block lock status change, for the subsequent read operation to reflect this change. 11. these specs are required only when the device is in a synchronous mode and clock is active during address setup phase.
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 36 251902-12 note: wait deasserted during asynchronous read and during write. wait high-z during write per oe# deasserted. figure 18: write to write timing w1 w7 w4 w7 w4 w3 w9 w3 w9 w3 w3 w6 w2 w6 w2 w8 w8 w5 w5 a ddress [a] ce# [e} we# [w] oe# [g] wait [t] data [d/q] rst# [p] figure 19: asynchronous read to write timing q d r5 w7 w4 r10 r7 r6 r1 7 r15 w6 w3 w3 w2 r9 r4 r8 r3 w8 w5 r1 r2 r1 a ddress [a] ce# [e} oe# [g] we # [w] wait [t] data [d/q] rst# [p]
november 2007 datasheet 251902-12 37 numonyx? strataflash ? wireless memory (l18) note: wait shown deasserted and high-z per oe# deassertion during write operation (rcr[10]=0 wait asserted low). clock is ignored during write operation. figure 20: write to asynchronous read timing d q w1 r9 r8 r4 r3 r2 w7 w4 r17 r15 w1 4 w18 w3 w3 r10 w6 w2 r1 r1 w8 w5 a d d re ss [ a ] adv# [v] ce# [e} we# [w] oe# [g] wait [t] data [d/q] rst# [p] figure 21: synchronous read to write timing lat ency c ount q d d w7 r 305 r 304 r7 r312 r 307 r16 w15 w22 w21 w9 w8 w9 w3 w22 w21 w3 w2 r8 r4 w6 r11 r13 r11 r303 r3 r 104 r 104 r106 r102 r105 r105 w18 w5 r101 r2 r306 r302 r301 clk [c] a ddress [a] adv# [v] ce# [e] oe# [g] we# wait [t] data [d/q]
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 38 251902-12 note: wait shown deasserted and high-z per oe# deassertion during write operation (rcr[10]=0 wait asserted low). 7.7 program and erase characteristics figure 22: write to synchronous read timing latency count d q q w1 r304 r305 r304 r3 w7 w4 r307 r15 r4 w20 w19 w18 w3 w3 r11 r303 r11 w6 w2 r104 r106 r104 r306 w8 w5 r302 r301 r2 clk a ddress [a] ad v# ce# [e} we# [w] oe# [ g] wait [t] data [d/q] rst# [p] table 17: program and erase specifications (sheet 1 of 2) nbr. symbol parameter v ppl v pph units note s min typ max min typ max conventional word programming w200 t prog/w program time single word - 90 180 - 85 170 s 1 single cell - 30 60 - 30 60 buffered programming w200 t prog/w program time single word - 90 180 - 85 170 s 1 w201 t prog/pb one buffer (32 words) - 440 880 - 340 680 buffered enhanced factory programming w451 t befp/w program single word n/a n/a n/a - 10 - s 1,2 w452 t befp/setup buffered efp setup n/a n/a n/a 5 - - 1 erasing and suspending
november 2007 datasheet 251902-12 39 numonyx? strataflash ? wireless memory (l18) w500 t ers/pb erase time 16-kword parameter - 0.4 2.5 - 0.4 2.5 s 1 w501 t ers/mb 64-kword main - 1.2 4 - 1.0 4 w600 t susp/p suspend latency program suspend - 20 25 - 20 25 s w601 t susp/e erase suspend - 20 25 - 20 25 notes: 1. typical values measured at t c = +25 c and nominal voltages. performance numbers are valid for all speed versions. excludes system overhead. sampled, but not 100% tested. 2. averaged over entire device. table 17: program and erase specifications (sheet 2 of 2) nbr. symbol parameter v ppl v pph units note s min typ max min typ max
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 40 251902-12 8.0 power and reset specifications 8.1 power up and down power supply sequencing is not required if vcc, vccq, and vpp are connected together; if vccq and/or vpp are not connected to the vcc supply, then v cc should attain v ccmin before applying vccq and vpp. device inputs should not be driven before supply voltage equals v ccmin. power supply transitions should only occur when rst# is low. this protects the device from accidental programming or erasure during power transitions. 8.2 reset asserting rst# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization may not occur. this is because the flash memory may be providing status information, instead of array data as expected. connect rst# to the same active-low reset signal used for cpu initialization. also, because the device is disabled when rst# is asserted, it ignores its control inputs during power-up/down. invalid bus conditions are masked, providing a level of memory protection. system designers should guard against spurious writes when v cc voltages are above v lko . because both we# and ce# must be asserted for a write operation, deasserting either signal inhibits writes to the device. the command user interface (cui) architecture provides additional protection because alteration of memory contents can only occur after successful completion of a two-step command sequence (see section 9.2, ?device commands? on page 44 ). table 18: reset specifications nbr. symbol parameter min max unit notes p1 t plph rst# pulse width low 100 - ns 1,2,3,4 p2 t plrh rst# low to device reset during erase - 25 s 1,3,4,7 rst# low to device reset during program - 25 1,3,4,7 p3 t vccph v cc power valid to rst# deassertion (high) 60 - 1,4,5,6 notes: 1. these specifications are valid for all device versions (packages and speeds). 2. the device may reset if t plph is < t plphmin , but this is not guaranteed. 3. not applicable if rst# is tied to vcc. 4. sampled, but not 100% tested. 5. if rst# is tied to the v cc supply, device will not be ready until t vccph after v cc v cc min. 6. if rst# is tied to any supply/signal with v ccq voltage levels, the rst# input voltage must not exceed v cc until v cc v cc (min). 7. reset completes within t plph if rst# is asserted while no erase or program operation is executing.
november 2007 datasheet 251902-12 41 numonyx? strataflash ? wireless memory (l18) 8.3 power supply decoupling flash memory devices require careful power supply decoupling. three basic power supply current considerations are: 1) standby current levels; 2) active current levels; and 3) transient peaks produced when ce# and oe# are asserted and deasserted. when the device is accessed, many internal conditions change. circuits within the device enable charge-pumps, and internal logic states change at high speed. all of these internal activities produce transient signals. transient current magnitudes depend on the device outputs? capacitive and inductive loading. two-line control and correct decoupling capacitor selection suppress transient voltage peaks. because numonyx multi-level cell (mlc) flash memory devices draw their power from vcc, vpp, and vccq, each power connection should have a 0.1 f ceramic capacitor connected to a corresponding ground conn ection. high-frequency, inherently low- inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices used in the system, a 4.7 f electrolytic capacitor should be placed between power and ground close to the devices. the bulk capacitor is meant to overcome voltage droop caused by pcb trace inductance. 8.4 automatic power saving automatic power saving (aps) provides low power operation during a read?s active state. i ccaps is the average current measured over any 5 ms time interval, 5 s after ce# is deasserted. during aps, average current is measured over the same time interval 5 s after the following events happen: (1) there is no internal read, program or erase operations cease; (2) ce# is asserted; (3) the address lines are quiescent and at v ssq or v ccq . oe# may also be driven during aps. figure 23: reset operation waveforms ( a) reset during read mode (b) reset during program or block erase p1 p2 (c) reset during program or block erase p1 p2 v ih v il v ih v il v ih v il rst# [p] rst# [p] rst# [p] abort complete abort complete v cc 0v v cc (d) vcc power-up to rst# high p1 r5 p2 p3 p2 r5 r5
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 42 251902-12 9.0 device operations this section provides an overview of device operations. the system cpu provides control of all in-system read, write, and erase operations of the device via the system bus. the on-chip write state machine (wsm) manages all block-erase and word- program algorithms. device commands are written to the command user interface (cui) to control all flash memory device operations. the cui does not occupy an addressable memory location; it is the mechanism through which the flash device is controlled. 9.1 bus operations ce#-low and rst#-high enable device read operations. the device internally decodes upper address inputs to determine the accessed partition. adv#-low opens the internal address latches. oe#-low activates the outputs and gates selected data onto the i/o bus. in asynchronous mode, the address is latched when adv# goes high or continuously flows through if adv# is held low. in synchronous mode, the address is latched by the first of either the rising adv# edge or the next valid clk edge with adv# low (we# and rst# must be vih; ce# must be vil). bus cycles to/from the l18 device conform to standard microprocessor bus operations. ta b l e 1 9 summarizes the bus operations and the logic levels that must be applied to the device?s control signal inputs. 9.1.1 reads to perform a read operation, rst# and we# must be deasserted while ce# and oe# are asserted. ce# is the device-select control. when asserted, it enables the flash memory device. oe# is the data-output control. when asserted, the addressed flash memory data is driven onto the i/o bus. see section 10.0, ?read operations? on page 48 for details on the available read modes, and see section 15.0, ?special read states? on page 73 for details regarding the available read states. table 19: bus operations summary bus operation rst# clk adv# ce# oe# we# wait dq[15:0 ] notes read asynchronous v ih xll l h deasserted output synchronous v ih running l l l h driven output burst suspend v ih halted x l h h high-z output write v ih x l l h l high-z input 1 output disable v ih x x l h h high-z high-z 2 standby v ih x x h x x high-z high-z 2 reset v il x x x x x high-z high-z 2,3 notes: 1. refer to the table 20, ?command bus cycles? on page 44 for valid dq[15:0] during a write operation. 2. x = don?t care (h or l). 3. rst# must be at v ss 0.2 v to meet the maximum specified power-down current.
november 2007 datasheet 251902-12 43 numonyx? strataflash ? wireless memory (l18) the automatic power savings (aps) feature provides low power operation following reads during active mode. after data is read from the memory array and the address lines are quiescent, aps automatically places the device into standby. in aps, device current is reduced to i ccaps (see section 6.1, ?dc current characteristics? on page 24 ). 9.1.2 writes to perform a write operation, both ce# and we# are asserted while rst# and oe# are deasserted. during a write operation, address and data are latched on the rising edge of we# or ce#, whichever occurs first. table 20, ?command bus cycles? on page 44 shows the bus cycle sequence for each of the supported device commands, while table 21, ?command codes and definitions? on page 45 describes each command. see section 7.0, ?ac characteristics? on page 26 for signal-timing details. note: write operations with invalid v cc and/or v pp voltages can produce spurious results and should not be attempted. 9.1.3 output disable when oe# is deasserted, device outputs dq[15:0] are disabled and placed in a high - impedance (high-z) state, wait is also placed in high-z. 9.1.4 standby when ce# is deasserted the device is deselected and placed in standby, substantially reducing power consumption. in standby, the data outputs are placed in high-z, independent of the level placed on oe#. standby current, i ccs , is the average current measured over any 5 ms time interval, 5 s after ce# is deasserted. during standby, average current is measured over the same time interval 5 s after ce# is deasserted. when the device is deselected (while ce# is deasserted) during a program or erase operation, it continues to consume active power until the program or erase operation is completed. 9.1.5 reset as with any automated device, it is important to assert rst# when the system is reset. when the system comes out of reset, the system processor attempts to read from the flash memory if it is the system boot device. if a cpu reset occurs with no flash memory reset, improper cpu initialization may occur because the flash memory may be providing status information rather than array data. flash memory devices from numonyx allow proper cpu initialization following a system reset through the use of the rst# input. rst# should be controlled by the same low-true reset signal that resets the system cpu. after initial power-up or reset, the device defaults to asynchronous read array, and the status register is set to 0x80. asserting rst# de-energizes all internal circuits, and places the output drivers in high-z. when rst# is asserted, the device shuts down the operation in progress, a process which takes a minimum amount of time to complete. when rst# has been deasserted, the device is reset to asynchronous read array state. note: if rst# is asserted during a program or erase operation, the operation is terminated and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, because the data may have been only partially written or erased.
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 44 251902-12 when returning from a reset (rst# deasserted), a minimum wait is required before the initial read access outputs valid data. also, a minimum delay is required after a reset before a write cycle can be initiated. after this wake - up interval passes, normal operation is restored. see section 7.0, ?ac characteristics? on page 26 for details about signal-timing. 9.2 device commands device operations are initiated by writing specific device commands to the command user interface (cui). see table 20, ?command bus cycles? on page 44 . several commands are used to modify array data including word program and block erase commands. writing either command to the cui initiates a sequence of internally - timed functions that culminate in the completion of the requested task. however, the operation can be aborted by either asserting rst# or by issuing an appropriate suspend command. table 20: command bus cycles (sheet 1 of 2) mode command bus cycles first bus cycle second bus cycle oper addr 1 data 2 oper addr 1 data 2 read read array 1 write pna 0xff read device identifier 2writepna0x90readpba+ia id cfi query 2writepna0x98readpna+qaqd read status register 2 write pna 0x70 read pna srd clear status register 1 write x 0x50 program word program 2 write wa 0x40/ 0x10 write wa wd buffered program 3 > 2writewa 0xe8write wa n - 1 buffered enhanced factory program (buffered efp) 4 > 2writewa0x80write wa 0xd0 erase block erase 2 write ba 0x20 write ba 0xd0 suspend program/erase suspend 1 write x 0xb0 program/erase resume 1 write x 0xd0 block locking/ unlocking lock block 2 write ba 0x60 write ba 0x01 unlock block 2 write ba 0x60 write ba 0xd0 lock-down block 2 write ba 0x60 write ba 0x2f
november 2007 datasheet 251902-12 45 numonyx? strataflash ? wireless memory (l18) 9.3 command definitions valid device command codes and descriptions are shown in ta b l e 2 1 . protection program protection register 2 write pra 0xc0 write pra pd program lock register 2 write lra 0xc0 write lra lrd configuration program read configuration register 2 write rcd 0x60 write rcd 0x03 notes: 1. first command cycle address should be the same as the operation?s target address. pna = address within the partition. pba = partition base address. ia = identification code address offset. qa = cfi query address offset. ba = address within the block. wa = word address of memory location to be written. pra = protection register address. lra = lock register address. x = any valid address within the device. 2. id = identifier data. qd = query data on dq[15:0]. srd = status register data. wd = word data. n = word count of data to be loaded into the write buffer. pd = protection register data. pd = protection register data. lrd = lock register data. rcd = read configuration register data on a[15:0]. a[max:16] can select any partition . 3. the second cycle of the buffered program command is the word count of the data to be loaded into the write buffer. this is followed by up to 32 words of data.then the confirm command (0xd0) is issued, triggering the array programming operation. 4. the confirm command (0xd0) is followed by the buffer data. table 20: command bus cycles (sheet 2 of 2) mode command bus cycles first bus cycle second bus cycle oper addr 1 data 2 oper addr 1 data 2 table 21: command codes and definitions (sheet 1 of 3) mode code device mode description read 0xff read array places the addressed partition in read array mode. array data is output on dq[15:0]. 0x70 read status register places the addressed partition in read status register mode. the partition enters this mode after a program or erase command is issued. status register data is output on dq[7:0]. 0x90 read device id or configuration register places the addressed partition in read device identifier mode. subsequent reads from addresses within the partition outputs manufacturer/device codes, configuration register data, block lock status, or protection register data on dq[15:0]. 0x98 read query places the addressed partition in read query mode. subsequent reads from the partition addresses output common flash interface information on dq[7:0]. 0x50 clear status register the wsm can only set status register error bits. the clear status register command is used to clear the sr error bits.
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 46 251902-12 write 0x40 word program setup first cycle of a 2-cycle programming command; prepares the cui for a write operation. on the next write cycle, the address and data are latched and the wsm executes the programming algorithm at the addressed location. during program operations, the partition responds only to read status register and program suspend commands. ce# or oe# must be toggled to update the status register in asynchronous read. ce# or adv# must be toggled to update the status register data for synchronous non-array read. the read array command must be issued to read array data after programming has finished. write 0x10 alternate word program setup equivalent to the word program setup command, 0x40. write 0xe8 buffered program this command loads a variable number of bytes up to the buffer size of 32 words onto the program buffer. write 0xd0 buffered program confirm the confirm command is issued after the data streaming for writing into the buffer is done. this instructs the wsm to perform the buffered program algorithm, writing the data from the buffer to the flash memory array. write 0x80 buffered enhanced factory programming setup first cycle of a 2-cycle command; initiates buffered enhanced factory program mode (buffered efp). the cui then waits for the buffered efp confirm command, 0xd0, that initiates the buffered efp algorithm. all other commands are ignored when buffered efp mode begins. write 0xd0 buffered efp confirm if the previous command was buffered efp setup (0x80), the cui latches the address and data, and prepares the device for buffered efp mode. erase 0x20 block erase setup first cycle of a 2-cycle command; prepares the cui for a block-erase operation. the wsm performs the erase algorithm on the block addressed by the erase confirm command. if the next command is not the erase confirm (0xd0) command, the cui sets status register bits sr[4] and sr[5], and places the addressed partition in read status register mode. 0xd0 block erase confirm if the first command was block erase setup (0x20), the cui latches the address and data, and the wsm erases the addressed block. during block-erase operations, the partition responds only to read status register and erase suspend commands. ce# or oe# must be toggled to update the status register in asynchronous read. ce# or adv# must be toggled to update the status register data for synchronous non-array read. suspend 0xb0 program or erase suspend this command issued to any device address initiates a suspend of the currently- executing program or block erase operation. the status register indicates successful suspend operation by setting either sr[2] (program suspended) or sr[6] (erase suspended), along with sr[7] (ready). the write state machine remains in the suspend mode regardless of control signal states (except for rst# asserted). 0xd0 suspend resume this command issued to any device address resumes the suspended program or block-erase operation. block locking/ unlocking 0x60 lock block setup first cycle of a 2-cycle command; prepares the cui for block lock configuration changes. if the next command is not block lock (0x01), block unlock (0xd0), or block lock-down (0x2f), the cui sets status register bits sr[4] and sr[5], indicating a command sequence error. 0x01 lock block if the previous command was block lock setup (0x60), the addressed block is locked. 0xd0 unlock block if the previous command was block lock setup (0x60), the addressed block is unlocked. if the addressed block is in a lock-down state, the operation has no effect. 0x2f lock-down block if the previous command was block lock setup (0x60), the addressed block is locked down. table 21: command codes and definitions (sheet 2 of 3) mode code device mode description
november 2007 datasheet 251902-12 47 numonyx? strataflash ? wireless memory (l18) protection 0xc0 program protection register setup first cycle of a 2-cycle command; prepares the device for a protection register or lock register program operation. the second cycle latches the register address and data, and starts the programming algorithm. configuration 0x60 read configuration register setup first cycle of a 2-cycle command; prepares the cui for device read configuration. if the set read configuration register command (0x03) is not the next command, the cui sets status register bits sr[4] and sr[5], indicating a command sequence error. 0x03 read configuration register if the previous command was read configuration register setup (0x60), the cui latches the address and writes a[15:0] to the read configuration register. following a configure read configuration register command, subsequent read operations access array data. table 21: command codes and definitions (sheet 3 of 3) mode code device mode description
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 48 251902-12 10.0 read operations the device supports two read modes: asynchronous page mode and synchronous burst mode. asynchronous page mode is the default read mode after device power-up or a reset. the read configuration register must be configured to enable synchronous burst reads of the flash memory array (see section 10.3, ?read configuration register (rcr)? on page 49 ). each partition of the device can be in any of four read states: read array, read identifier, read status or read query. upon power-up, or after a reset, all partitions of the device default to read array. to change a partition?s read state, the appropriate read command must be written to the device (see section 9.2, ?device commands? on page 44 ). see section 15.0, ?special read states? on page 73 for details regarding read status, read id, and cfi query modes. the following sections describe read-mode operations in detail. 10.1 asynchronous page-mode read following a device power-up or reset, asynchronous page mode is the default read mode and all partitions are set to read array. however, to perform array reads after any other device operation (e.g. write operation), the read array command must be issued in order to read from the flash memory array. note: asynchronous page-mode reads can only be performed when read configuration register bit rcr[15] is set ( see section 10.3, ?read configuration register (rcr)? on page 49 ). to perform an asynchronous page-mode read, an address is driven onto a[max:0], and ce# and adv# are asserted. we# and rst# must already have been deasserted. wait is deasserted during asynchronous page mode. adv# can be driven high to latch the address, or it must be held low throughout the read cycle. clk is not used for asynchronous page-mode reads, and is ignored. if only asynchronous reads are to be performed, clk should be tied to a valid v ih level, wait signal can be floated and adv# must be tied to ground. array data is driven onto dq[15:0] after an initial access time t avqv delay. (see section 7.0, ?ac characteristics? on page 26 ). in asynchronous page mode, four data words are ?sensed? simultaneously from the flash memory array and loaded into an internal page buffer. the buffer word corresponding to the initial address on a[max:0] is driven onto dq[15:0] after the initial access delay. address bits a[max:2] select the 4-word page. address bits a[1:0] determine which word of the 4-word page is output from the data buffer at any given time. 10.2 synchronous burst-mode read to pe rfo rm a synchronous burst- read, an initial address is driven onto a[max:0], and ce# and adv# are asserted. we# and rst# must already have been deasserted. adv# is asserted, and then deasserted to latch the address. alternately, adv# can remain asserted throughout the burst access, in which case the address is latched on the next valid clk edge while adv# is asserted. during synchronous array and non-array read modes, the first word is output from the data buffer on the next valid clk edge after the initial access latency delay (see section 10.3.2, ?latency count? on page 50 ). subsequent data is output on valid clk edges following a minimum delay. however, for a synchronous non-array read, the same word of data will be output on successive clock edges until the burst length requirements are satisfied.
november 2007 datasheet 251902-12 49 numonyx? strataflash ? wireless memory (l18) 10.2.1 burst suspend the burst suspend feature of the device can reduce or eliminate the initial access latency incurred when system software needs to suspend a burst sequence that is in progress in order to retrieve data from another device on the same system bus. the system processor can resume the burst sequence later. burst suspend provides maximum benefit in non-cache systems. burst accesses can be suspended during the initial access latency (before data is received) or after the device has output data. when a burst access is suspended, internal array sensing continues and any previously latched internal data is retained. a burst sequence can be suspended and resumed without limit as long as device operation conditions are met. burst suspend occurs when ce# is asserted, the current address has been latched (either adv# rising edge or valid clk edge), clk is halted, and oe# is deasserted. clk can be halted when it is at v ih or v il . wait is in high-z during oe# deassertion. to resume the burst access, oe# is reasserted, and clk is restarted. subsequent clk edges resume the burst sequence. within the device, ce# and oe# gate wait. therefore, during burst suspend wait is placed in high-impedance state when oe# is deasserted and resumed active when oe# is re-asserted. see figure 17, ?burst suspend timing? on page 34 . 10.3 read configuration register (rcr) the rcr is used to select the read mode (synchronous or asynchronous), and it defines the synchronous burst characteristics of the device. to modify rcr settings, use the configure read configuration register command (see section 9.2, ?device commands? on page 44 ). rcr contents can be examined using the read device identifier command, and then reading from + 0x05 (see section 15.2, ?read device identifier? on page 74 ). the rcr is shown in ta b l e 2 2 . the following sections describe each rcr bit. table 22: read configuration register description (sheet 1 of 2) read configuration register (rcr) read mode res latency count wait polarity data hold wait delay burst seq clk edge res res burst wrap burst length rm r lc[2:0] wp dh wd bs ce r r bw bl[2:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name description 15 read mode (rm) 0 = synchronous burst-mode read 1 = asynchronous page-mode read (default) 14 reserved (r) reserved bits should be cleared (0) 13:11 latency count (lc[2:0]) 010 =code 2 011 =code 3 100 =code 4 101 =code 5 110 =code 6 111 =code 7 (default) (other bit settings are reserved)
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 50 251902-12 10.3.1 read mode the read mode (rm) bit selects synchronous burst-mode or asynchronous page-mode operation for the device. when the rm bit is set, asynchronous page mode is selected (default). when rm is cleared, synchronous burst mode is selected. 10.3.2 latency count the latency count bits, lc[2:0], tell the device how many clock cycles must elapse from the rising edge of adv# (or from the first valid clock edge after adv# is asserted) until the first data word is to be driven onto dq[15:0]. the input clock frequency is used to determine this value. figure 24 shows the data output latency for the different settings of lc[2:0]. synchronous burst with a latency count setting of code 4 will result in zero wait state; however, a latency count setting of code 5 will cause 1 wait state (code 6 will cause 2 wait states, and code 7 will cause 3 wait states) after every four words, regardless of whether a 16-word boundary is crossed. if rcr[9] (data hold) bit is set (data hold of two clocks) this wait condition will not occur because enough clocks elapse during each burst cycle to eliminate subsequent wait states. refer to ta b l e 2 3 and ta b l e 2 4 for latency code settings. 10 wait polarity (wp) 0 =wait signal is active low 1 =wait signal is active high (default) 9 data hold (dh) 0 =data held for a 1-clock data cycle 1 =data held for a 2-clock data cycle (default) 8 wait delay (wd) 0 =wait deasserted with valid data 1 =wait deasserted one data cycle before valid data (default) 7 burst sequence (bs) 0 =reserved 1 =linear (default) 6 clock edge (ce) 0 = falling edge 1 = rising edge (default) 5:4 reserved (r) reserved bits should be cleared (0) 3 burst wrap (bw) 0 =wrap; burst accesses wrap within burst length set by bl[2:0] 1 =no wrap; burst accesses do not wrap within burst length (default) 2:0 burst length (bl[2:0]) 001 =4-word burst 010 =8-word burst 011 =16-word burst 111 =continuous-word burst (default) (other bit settings are reserved) note: latency code 2, data hold for a 2-clock data cycle (dh = 1) wait must be deasserted with valid data (wd = 0). wd = 1 is not supported. table 22: read configuration register description (sheet 2 of 2)
november 2007 datasheet 251902-12 51 numonyx? strataflash ? wireless memory (l18) see figure 25, ?example latency count setting? on page 52 . figure 24: first-access latency count table 23: lc and frequency support (t avqv /t chqv = 85 ns / 14 ns) v ccq = 1.7 v to 2.0 v latency count settings frequency support (mhz) 2< 28 3< 40 4, 5, 6 or 7 < 54 table 24: lc and frequency support (t avqv /t chqv = 90 ns / 17 ns) v ccq = 1.35 v to 2.0 v latency count settings frequency support (mhz) 2< 27 3, 4, 5, 6 or 7 < 40 code 1 (reserved code 6 code 5 code 4 code 3 code 2 code 0 (reserved) code 7 valid address valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output address [a] adv# [v] dq 15-0 [d/q] clk [c] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q]
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 52 251902-12 10.3.3 wait polarity the wait polarity bit (wp), rcr[10] determines the asserted level (v oh or v ol ) of wait. when wp is set, wait is asserted-high (default). when wp is cleared, wait is asserted-low. wait changes state on valid clock edges during active bus cycles (ce# asserted, oe# asserted, rst# deasserted). 10.3.3.1 wait signal function the wait signal indicates data valid when the device is operating in synchronous mode (rcr[15]=0). the wait signal is only ?deasserted? when data is valid on the bus. when the device is operating in synchronous non-array read mode, such as read status, read id, or read query the wait signal is also ?deasserted? when data is valid on the bus. wait behavior during synchronous non-array reads at the end of word line works correctly only on the first data access. when the device is operating in asynchronous page mode, asynchronous single word read mode, and all write operations, wait is set to a deasserted state as determined by rcr[10]. see figure 12, ?asynchronous single-word read with adv# latch? on page 32 , and figure 13, ?asynchronous page-mode read timing? on page 32 . figure 25: example latency count setting clk ce# adv# a[max:0] d[15:0] t data code 3 address data 012 34 r103 high-z
november 2007 datasheet 251902-12 53 numonyx? strataflash ? wireless memory (l18) 10.3.4 data hold for burst read operations, the data hold (dh) bit determines whether the data output remains valid on dq[15:0] for one or two-clock cycles. this period of time is called the ?data cycle?. when dh is set, output data is held for two clocks (default). when dh is cleared, output data is held for one clock (see figure 26 ). the processor?s data setup time and the flash memory?s clock-to-data output delay should be considered when determining whether to hold output data for one or two clocks. a method for determining the data hold configuration is shown below: to set the device at one clock data hold for subsequent reads, the following condition must be satisfied: t chqv (ns) + t data (ns) one clk period (ns) t data = data set up to clock (defined by cpu) for example, with a clock frequency of 40 mhz, the clock period is 25 ns. assuming t chqv = 20 ns and t data = 4ns. applying these values to the formula above: 20 ns + 4 ns 25 ns the equation is satisfied and data will be available at every clock period with data hold setting at one clock. if t chqv (ns) + t data (ns) > one clk period (ns), data hold setting of 2 clock periods must be used. table 25: wait functionality table condition wait notes ce# = ?1?, oe# = ?x? ce# = ?x?, oe# = ?1? high-z 1 ce# =?0?, oe# = ?0? active 1 synchronous array reads active 1 synchronous non-array reads active 1 all asynchronous reads deasserted 1 all writes high-z 1,2 notes: 1. active: wait is asserted until data becomes valid, then deasserts 2. when oe# = v ih during writes, wait = high-z
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 54 251902-12 10.3.5 wait delay the wait delay (wd) bit controls the wait assertion-delay behavior during synchronous burst reads. wait can be asserted either during or one data cycle before invalid data is output on dq[15:0]. when wd is set, wait is asserted one data cycle before invalid data (default). when wd is cleared, wait is asserted during invalid data. 10.3.6 burst sequence the burst sequence (bs) bit selects linear-burst sequence (default). only linear-burst sequence is supported. ta b l e 2 6 shows the synchronous burst sequence for all burst lengths, as well as the effect of the burst wrap (bw) setting. figure 26: data hold timing valid output valid output valid output valid output valid output clk [c] d[15:0] [q] d[15:0] [q] 2 clk data hold 1 clk data hold table 26: burst sequence word ordering (sheet 1 of 2) start addr. (dec) burst wrap (rcr[3]) burst addressing sequence (dec) 4-word burst (bl[2:0] = 0b001) 8-word burst (bl[2:0] = 0b010) 16-word burst (bl[2:0] = 0b011) continuous burst (bl[2:0] = 0b111) 0 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4?14-15 0-1-2-3-4-5-6-? 1 0 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5?15-0 1-2-3-4-5-6-7-? 2 0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6?15-0-1 2-3-4-5-6-7-8-? 3 0 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7?15-0-1-2 3-4-5-6-7-8-9-? 40 4-5-6-7-0-1-2-3 4-5-6-7-8?15-0-1-2-3 4-5-6-7-8-9-10? 50 5-6-7-0-1-2-3-4 5-6-7-8-9?15-0-1-2-3-4 5-6-7-8-9-10-11? 60 6-7-0-1-2-3-4-5 6-7-8-9-10?15-0-1-2-3-4- 5 6-7-8-9-10-11-12-? 70 7-0-1-2-3-4-5-6 7-8-9-10?15-0-1-2-3-4-5- 6 7-8-9-10-11-12-13? ? ? ? ? ? ? 14 0 14-15-0-1-2?12-13 14-15-16-17-18-19-20-? 15 0 15-0-1-2-3?13-14 15-16-17-18-19-20-21-? ? ? ? ? ? ? 0 1 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4?14-15 0-1-2-3-4-5-6-? 1 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5?15-16 1-2-3-4-5-6-7-?
november 2007 datasheet 251902-12 55 numonyx? strataflash ? wireless memory (l18) 10.3.7 clock edge the clock edge (ce) bit selects either a rising (default) or falling clock edge for clk. this clock edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert wait. 10.3.8 burst wrap the burst wrap (bw) bit determines whether 4-word, 8-word, or 16-word burst length accesses wrap within the selected word-length boundaries or cross word-length boundaries. when bw is set, burst wrapping does not occur (default). when bw is cleared, burst wrapping occurs. when performing synchronous burst reads with bw set (no wrap), an output delay may occur when the burst sequence crosses its fi rst device-row (16-word) boundary. if the burst sequence?s start address is 4-word aligned, then no delay occurs. if the start address is at the end of a 4-word boundary, the worst case output delay is one clock cycle less than the first access latency count. this delay can take place only once, and doesn?t occur if the burst sequence does not cross a device-row boundary. wait informs the system of this delay when it occurs. 10.3.9 burst length the burst length bit (bl[2:0]) selects the linear burst length for all synchronous burst reads of the flash memory array. the burst lengths are 4-word, 8-word, 16-word, and continuous word. continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see table 26, ?burst sequence word ordering? on page 54 ). when a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the ?burstable? address space. 2 1 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6?16-17 2-3-4-5-6-7-8-? 3 1 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7?17-18 3-4-5-6-7-8-9-? 41 4-5-6-7-8-9-10-11 4-5-6-7-8?18-19 4-5-6-7-8-9-10? 51 5-6-7-8-9-10-11-12 5-6-7-8-9?19-20 5-6-7-8-9-10-11? 61 6-7-8-9-10-11-12-13 6-7-8-9-10?20-21 6-7-8-9-10-11-12-? 71 7-8-9-10-11-12-13- 14 7-8-9-10-11?21-22 7-8-9-10-11-12-13? ? ? ? ? ? ? 14 1 14-15-16-17-18?28-29 14-15-16-17-18-19-20-? 15 1 15-16-17-18-19?29-30 15-16-17-18-19-20-21-? table 26: burst sequence word ordering (sheet 2 of 2)
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 56 251902-12 11.0 programming operations the device supports three programming methods: word programming (40h/10h), buffered programming (e8h, d0h), and buffered enhanced factory programming (buffered efp) (80h, d0h). see section 9.0, ?device operations? on page 42 for details on the various programming commands issued to the device. successful programming requires the addressed block to be unlocked. if the block is locked down, wp# must be deasserted and the block must be unlocked before attempting to program the block. attempting to program a locked block causes a program error (sr[4] and sr[1] set) and termination of the operation. see section 13.0, ?security modes? on page 64 for details on locking and unlocking blocks. the following sections describe device programming in detail. 11.1 word programming word programming operations are initiated by writing the word program setup command to the device (see section 9.0, ?device operations? on page 42 ). this is followed by a second write to the device with the address and data to be programmed. the partition accessed during both write cycles outputs status register data when read. the partition accessed during the second cycle (the data cycle) of the program command sequence is the location where the data is written. see figure 39, ?word program flowchart? on page 83 . programming can occur in only one partition at a time; all other partitions must be in a read state or in erase suspend. v pp must be above v pplk , and within the specified v ppl min/max values (nominally 1.8 v). during programming, the write state machine (wsm) executes a sequence of internally-timed events that program the desired data bits at the addressed location, and verifies that the bits are sufficiently programmed. programming the flash memory array changes ?ones? to ?zeros.? memory array bits that are zeros can be changed to ones only by erasing the block (see section 12.0, ?erase operations? on page 62 ). the status register can be examined for programming progress and errors by reading any address within the partition that is being programmed. the partition remains in the read status register state until another command is written to that partition. issuing the read status register command to another partition address sets that partition to the read status register state, allowing programming progress to be monitored at that partition?s address. status register bit sr[7] indicates the programming status while the sequence executes. commands that can be issued to the programming partition during programming are program suspend, read status register, read device identifier, cfi query, and read array (this returns unknown data). when programming has finished, status register bit sr[4] (when set) indicates a programming failure. if sr[3] is set, the wsm could not perform the word programming operation because v pp was outside of its acceptable limits. if sr[1] is set, the word programming operation attempted to program a locked block, causing the operation to abort. before issuing a new command, the status register contents should be examined and then cleared using the clear status register command. any valid command can follow, when word programming has completed.
november 2007 datasheet 251902-12 57 numonyx? strataflash ? wireless memory (l18) 11.1.1 factory word programming factory word programming is similar to word programming in that it uses the same commands and programming algorithms. however, factory word programming enhances the programming performance with v pp = v pph . this can enable faster programming times during oem manufacturing processes. factory word programming is not intended for extended use. see section 5.2, ?operating conditions? on page 23 for limitations when v pp = v pph . note: when v pp = v ppl , the device draws programming current from the v cc supply. if v pp is driven by a logic signal, v ppl must remain above v ppl min to program the device. when v pp = v pph , the device draws programming current from the v pp supply. figure 27, ?example vpp supply connections? on page 61 shows examples of device power supply configurations. 11.2 buffered programming the device features a 32-word buffer to enable optimum programming performance. for buffered programming, data is first written to an on-chip write buffer. then the buffer data is programmed into the flash memory array in buffer-size increments. this can improve system programming performance significantly over non-buffered programming. when the buffered programming setup command is issued (see section 9.2, ?device commands? on page 44 ), status register information is updated and reflects the availability of the write buffer. sr[7] indicates buffer availability: if set, the buffer is available; if cleared, the write buffer is not available. to retry, issue the buffered programming setup command again, and re-check sr[7]. when sr[7] is set, the buffer is ready for loading. (see figure 41, ?buffer program flowchart? on page 85 ). on the next write, a word count is written to the device at the buffer address. this tells the device how many data words will be written to the buffer, up to the maximum size of the buffer. on the next write, a device start address is given along with the first data to be written to the flash memory array. subsequent writes provide additional device addresses and data. all data addresses must lie within the start address plus the word count. optimum programming performance and lower power usage are obtained by aligning the starting address at the beginning of a 32-word boundary (a[4:0] = 0x00). crossing a 32-word boundary during programming will double the total programming time. after the last data is written to the buffer, the buffered programming confirm command must be issued to the original block address. the wsm begins to program buffer contents to the flash memory array. if a command other than the buffered programming confirm command is written to the device, a command sequence error occurs and status register bits sr[7,5,4] are set. if an error occurs while writing to the array, the device stops programming, and status register bits sr[7,4] are set, indicating a programming failure. reading from another partition is allowed while data is being programmed into the array from the write buffer (see section 14.0, ?dual-operation considerations? on page 69 ). when buffered programming has completed, additional buffer writes can be initiated by issuing another buffered programming setup command and repeating the buffered program sequence. buffered programming may be performed with v pp = v ppl or v pph (see section 5.2, ?operating conditions? on page 23 for limitations when operating the device with v pp = v pph ).
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 58 251902-12 if an attempt is made to program past an erase-block boundary using the buffered program command, the device aborts the operation. this generates a command sequence error, and status register bits sr[5,4] are set. if buffered programming is attempted while v pp is below v pplk , status register bits sr[4,3] are set. if any errors are detected that have set status register bits, the status register should be cleared using the clear status register command. 11.3 buffered enhanced factory programming buffered enhanced factory programing (buffered efp) speeds up multi-level cell (mlc) flash programming for today's beat-rate-sensitive manufacturing environments. the enhanced programming algorithm used in buffered efp eliminates traditional programming elements that drive up overhead in device programmer systems. buffered efp consists of three phases: setup, program/verify, and exit (see figure 42, ?buffered efp flowchart? on page 86 ). it uses a write buffer to spread mlc program performance across 32 data words. verification occurs in the same phase as programming to accurately program the flash memory cell to the correct bit state. a single two-cycle command sequence programs the entire block of data. this enhancement eliminates three write cycles per buffer: two commands and the word count for each set of 32 data words. host programmer bus cycles fill the device?s write buffer followed by a status check. sr[0] indicates when data from the buffer has been programmed into sequential flash memory array locations. following the buffer-to-flash array programming sequence, the write state machine (wsm) increments internal addressing to automatically select the next 32-word array boundary. this aspect of buffered efp saves host programming equipment the address- bus setup overhead. with adequate continuity testing, programming equipment can rely on the wsm?s internal verification to ensure that the device has programmed properly. this eliminates the external post-program verification and its associated overhead. 11.3.1 buffered efp requirements and considerations buffered efp requirements: ? ambient temperature: t a = 25 c, 5 c ?v cc within specified operating range. ? vpp driven to v pph . ? target block unlocked before issuing the buffered efp setup and confirm commands. ? the first-word address (wa0) for the block to be programmed must be held constant from the setup phase through all data streaming into the target block, until transition to the exit phase is desired. ? wa0 must align with the start of an array buffer boundary 1 . buffered efp considerations: ? for optimum performance, cycling must be limited below 100 erase cycles per block 2 . ? buffered efp programs one block at a time; all buffer data must fall within a single block 3 . ? buffered efp cannot be suspended. ? programming to the flash memory array can occur only when the buffer is full 4 .
november 2007 datasheet 251902-12 59 numonyx? strataflash ? wireless memory (l18) ? read operation while performing buffered efp is not supported. notes: 1. word buffer boundaries in the array are determined by a[4:0] (0x00 through 0x1f). the alignment start point is a[4:0] = 0x00. 2. some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work properly. 3. if the internal address counter increments beyond the block's maximum address, addressing wraps around to the beginning of the block. 4. if the number of words is less than 32, remaining locations must be filled with 0xffff. 11.3.2 buffered efp setup phase after receiving the buffered efp setup and confirm command sequence, status register bit sr[7] (ready) is cleared, indicating that the wsm is busy with buffered efp algorithm startup. a delay before checking sr[7] is required to allow the wsm enough time to perform all of its setups and checks (block-lock status, v pp level, etc.). if an error is detected, sr[4] is set and buffered efp operation terminates. if the block was found to be locked, sr[1] is also set. sr[3] is set if the error occurred due to an incorrect v pp level. note: reading from the device after the buffered efp setup and confirm command sequence outputs status register data. do not issue the read status register command; it will be interpreted as data to be loaded into the buffer. 11.3.3 buffered efp program/verify phase after the buffered efp setup phase has completed, the host programming system must check sr[7,0] to determine the availability of the write buffer for data streaming. sr[7] cleared indicates the device is busy and the buffered efp program/verify phase is activated. sr[0] indicates the write buffer is available. two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data programming to the array. for buffered efp, the count value for buffer loading is always the maximum buffer size of 32 words. during the buffer-loading sequence, data is stored to sequential buffer locations starting at address 0x00. programming of the buffer contents to the flash memory array starts as soon as the buffer is full. if the number of words is less than 32, the remaining buffer locations must be filled with 0xffff. caution: the buffer must be completely filled for programming to occur. supplying an address outside of the current block's range during a buffer-fill sequence causes the algorithm to exit immediately. any data previously loaded into the buffer during the fill cycle is not programmed into the array. the starting address for data entry must be buffer size aligned, if not the buffered efp algorithm will be aborted and the program fail (sr[4]) flag will be set. data words from the write buffer are directed to sequential memory locations in the flash memory array; programming continues from where the previous buffer sequence ended. the host programming system must poll sr[0] to determine when the buffer program sequence completes. sr[0] cleared indicates that all buffer data has been transferred to the flash array; sr[0] set indicates that the buffer is not available yet for the next fill cycle. the host system may check full status for errors at any time, but it is only necessary on a block basis after buffered efp exit. after the buffer fill cycle, no write cycles should be issued to the device until sr[0] = 0 and the device is ready for the next buffer fill. note: any spurious writes are ignored after a buffer fill operation and when internal program is proceeding.
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 60 251902-12 the host programming system continues the buffered efp algorithm by providing the next group of data words to be written to the buffer. alternatively, it can terminate this phase by changing the block address to one outside of the current block?s range. the program/verify phase concludes when the programmer writes to a different block address; data supplied must be 0xffff. upon program/verify phase completion, the device enters the buffered efp exit phase. 11.3.4 buffered efp exit phase when sr[7] is set, the device has returned to normal operating conditions. a full status check should be performed on the partition being programmed at this time to ensure the entire block programmed successfully. when exiting the buffered efp algorithm with a block address change, the read mode of both the programmed and the addressed partition will not change. after buffered efp exit, any valid command can be issued to the device. 11.4 program suspend issuing the program suspend command while programming suspends the programming operation. this allows data to be accessed from memory locations other than the one being programmed. the program suspend command can be issued to any device address; the corresponding partition is not affected. a program operation can be suspended to perform reads only. additionally, a program operation that is running during an erase suspend can be suspended to perform a read operation (see figure 40, ?program suspend/resume flowchart? on page 84 ). when a programming operation is executing, issuing the program suspend command requests the wsm to suspend the programming algorithm at predetermined points. the partition that is suspended continues to output status register data after the program suspend command is issued. programming is suspended when status register bits sr[7,2] are set. suspend latency is specified in section 7.7, ?program and erase characteristics? on page 38 . to read data from blocks within the suspended partition, the read array command must be issued to that partition. read array, read status register, read device identifier, cfi query, and program resume are valid commands during a program suspend. a program operation does not need to be suspended in order to read data from a block in another partition that is not programming. if the other partition is already in a read array, read device identifier, or cfi query state, issuing a valid address returns corresponding read data. if the other partition is not in a read mode, one of the read commands must be issued to the partition before data can be read. during a program suspend, deasserting ce# places the device in standby, reducing active current. v pp must remain at its programming level, and wp# must remain unchanged while in program suspend. if rst# is asserted, the device is reset. 11.5 program resume the resume command instructs the device to continue programming, and automatically clears status register bits sr[7,2]. this command can be written to any partition. when read at the partition that?s programming, the device outputs data corresponding to the partition?s last state. if error bits are set, the status register should be cleared before issuing the next instruction. rst# must remain deasserted (see figure 40, ?program suspend/resume flowchart? on page 84 ).
november 2007 datasheet 251902-12 61 numonyx? strataflash ? wireless memory (l18) 11.6 program protection when v pp = v il , absolute hardware write protection is provided for all device blocks. if v pp is below v pplk , programming operations halt and sr[3] is set indicating a v pp -level error. block lock registers are not affected by the voltage level on v pp ; they may still be programmed and read, even if v pp is less than v pplk . figure 27: example vpp supply connections ? factory programming with v pp = v pph ? complete write/erase protection when v pp v pplk vcc vpp vcc vpp ? low voltage and factory programming ? low-voltage programming only ? logic control of device protection vcc vpp ? low voltage programming only ? full device protection unavailable vcc vpp 10k v pp v cc v cc prot # v cc v pp =v pph v cc
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 62 251902-12 12.0 erase operations flash erasing is performed on a block basis. an entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. when a block is erased, all bits within that block read as logical ones. the following sections describe block erase operations in detail. 12.1 block erase block erase operations are initiated by writing the block erase setup command to the address of the block to be erased (see section 9.2, ?device commands? on page 44 ). next, the block erase confirm command is written to the address of the block to be erased. erasing can occur in only one partition at a time; all other partitions must be in a read state. if the device is placed in standby (ce# deasserted) during an erase operation, the device completes the erase operation before entering standby.v pp must be above v pplk and the block must be unlocked (see figure 43, ?block erase flowchart? on page 87 ). during a block erase, the write state machine (wsm) executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block. erasing the flash memory array changes ?zeros? to ?ones.? memory array bits that are ones can be changed to zeros only by programming the block (see section 11.0, ?programming operations? on page 56 ). the status register can be examined for block erase progress and errors by reading any address within the partition that is being erased. the partition remains in the read status register state until another command is written to that partition. issuing the read status register command to another partition address sets that partition to the read status register state, allowing erase progress to be monitored at that partition?s address. sr[0] indicates whether the addressed partition or another partition is erasing. the partition?s status register bit sr[7] is set upon erase completion. status register bit sr[7] indicates block erase status while the sequence executes. when the erase operation has finished, status register bit sr[5] indicates an erase failure if set. sr[3] set would indicate that the wsm could not perform the erase operation because v pp was outside of its acceptable limits. sr[1] set indicates that the erase operation attempted to erase a locked block, causing the operation to abort. before issuing a new command, the status register contents should be examined and then cleared using the clear status register command. any valid command can follow once the block erase operation has completed. 12.2 erase suspend issuing the erase suspend command while erasing suspends the block erase operation. this allows data to be accessed from memory locations other than the one being erased. the erase suspend command can be issued to any device address; the corresponding partition is not affected. a block erase operation can be suspended to perform a word or buffer program operation, or a read operation within any block except the block that is erase suspended (see figure 40, ?program suspend/resume flowchart? on page 84 ). when a block erase operation is executing, issuing the erase suspend command requests the wsm to suspend the erase algorithm at predetermined points. the partition that is suspended continues to output status register data after the erase suspend command is issued. block erase is suspended when status register bits sr[7,6] are set. suspend latency is specified in section 7.7, ?program and erase characteristics? on page 38 .
november 2007 datasheet 251902-12 63 numonyx? strataflash ? wireless memory (l18) to read data from blocks within the suspended partition (other than an erase- suspended block), the read array command must be issued to that partition first. during erase suspend, a program command can be issued to any block other than the erase-suspended block. block erase cannot resume until program operations initiated during erase suspend complete. read array, read status register, read device identifier, cfi query, and erase resume are valid commands during erase suspend. additionally, clear status register, program, program suspend, block lock, block unlock, and block lock-down are valid commands during erase suspend. to read data from a block in a partition that is not erasing, the erase operation does not need to be suspended. if the other partition is already in read array, read device identifier, or cfi query, issuing a valid address returns corresponding data. if the other partition is not in a read state, one of the read commands must be issued to the partition before data can be read. during an erase suspend, deasserting ce# places the device in standby, reducing active current. v pp must remain at a valid level, and wp# must remain unchanged while in erase suspend. if rst# is asserted, the device is reset. 12.3 erase resume the erase resume command instructs the device to continue erasing, and automatically clears status register bits sr[7,6]. this command can be written to any partition. when read at the partition that?s erasing, the device outputs data corresponding to the partition?s last state. if status register error bits are set, the status register should be cleared before issuing the next instruction. rst# must remain deasserted (see figure 40, ?program suspend/resume flowchart? on page 84 ). 12.4 erase protection when v pp = v il , absolute hardware erase protection is provided for all device blocks. if v pp is below v pplk , erase operations halt and sr[3] is set indicating a v pp -level error.
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 64 251902-12 13.0 security modes the device features security modes used to protect the information stored in the flash memory array. the following sections describe each security mode in detail. 13.1 block locking individual instant block locking is used to protect user code and/or data within the flash memory array. all blocks power up in a locked state to protect array data from being altered during power transitions. any block can be locked or unlocked with no latency. locked blocks cannot be programmed or erased; they can only be read. software-controlled security is implemented using the block lock and block unlock commands. hardware-controlled security can be implemented using the block lock- down command along with asserting wp#. also, v pp data security can be used to inhibit program and erase operations (see section 11.6, ?program protection? on page 61 and section 12.4, ?erase protection? on page 63 ). 13.1.1 lock block to lock a block, issue the lock block setup command. the next command must be the lock block command issued to the desired block?s address (see section 9.2, ?device commands? on page 44 and figure 45, ?block lock operations flowchart? on page 89 ). if the set read configuration register command is issued after the block lock setup command, the device configures the rcr instead. block lock and unlock operations are not affected by the voltage level on v pp . the block lock bits may be modified and/or read even if v pp is below v pplk . 13.1.2 unlock block the unlock block command is used to unlock blocks (see section 9.2, ?device commands? on page 44 ). unlocked blocks can be read, programmed, and erased. unlocked blocks return to a locked state when the device is reset or powered down. if a block is in a lock-down state, wp# must be deasserted before it can be unlocked (see figure 28, ?block locking state diagram? on page 65 ). 13.1.3 lock-down block a locked or unlocked block can be locked-down by writing the lock-down block command sequence (see section 9.2, ?device commands? on page 44 ). blocks in a lock-down state cannot be programmed or erased; they can only be read. however, unlike locked blocks, their locked state cannot be changed by software commands alone. a locked-down block can only be unlocked by issuing the unlock block command with wp# deasserted. to return an unlocked block to locked-down state, a lock-down command must be issued prior to changing wp# to v il . locked-down blocks revert to the locked state upon reset or power up the device (see figure 28, ?block locking state diagram? on page 65 ).
november 2007 datasheet 251902-12 65 numonyx? strataflash ? wireless memory (l18) 13.1.4 block lock status the read device identifier command is used to determine a block?s lock status (see section 15.2, ?read device identifier? on page 74 ). data bits dq[1:0] display the addressed block?s lock status; dq0 is the addressed block?s lock bit, while dq1 is the addressed block?s lock-down bit. 13.1.5 block locking during suspend block lock and unlock changes can be performed during an erase suspend. to change block locking during an erase operation, first issue the erase suspend command. monitor the status register until sr[7] and sr[6] are set, indicating the device is suspended and ready to accept another command. next, write the desired lock command sequen ce to a block, which changes the lock state of that block. after completing block lock or unlock operations, resume the erase operation using the erase resume command. note: a lock block setup command followed by any command other than lock block, unlock block, or lock-down block produces a command sequence error and set status register bits sr[4] and sr[5]. if a command sequence error occurs during an erase suspend, sr[4] and sr[5] remains set, even after the erase operation is resumed. unless the status register is cleared using the clear status register command before resuming the erase operation, possible erase errors may be masked by the command sequence error. figure 28: block locking state diagram [x00] [x01] power-up/reset unlocked locked [011] [111] [110] locked- down 4,5 software locked [011] hardware locked 5 unlocked wp# hardware control notes: 1. [a,b,c] represents [wp#, dq1, dq0]. x = don?t care. 2. dq1 indicates block lock-down status. dq1 = ?0?, lock-down has not been issued to this block. dq1 = ?1?, lock-down has been issued to this block. 3. dq0 indicates block lock status. dq0 = ?0?, block is unlocked. dq0 = ?1?, block is locked. 4. locked-down = hardware + software locked. 5. [011] states should be tracked by system software to determine difference between hardware locked and locked-down states. software block lock (0x60/0x01) or software block unlock (0x60/0xd0) software block lock-down (0x60/0x2f) wp# hardware control
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 66 251902-12 if a block is locked or locked-down during an erase suspend of the same block, the lock status bits change immediately. however, the erase operation completes when it is resumed. block lock operations cannot occur during a program suspend. see appendix a, ?write state machine (wsm)? on page 76 , which shows valid commands during an erase suspend. 13.2 protection registers the device contains 17 protection registers (prs) that can be used to implement system security measures and/or device identification. each protection register can be individually locked. the first 128-bit protection register is comprised of two 64-bit (8-word) segments. the lower 64-bit segment is pre-programmed at the factory with a unique 64-bit number. the other 64-bit segment, as well as the other sixteen 128-bit protection registers, are blank. users can program these registers as needed. when programmed, users can then lock the protection register(s) to prevent additional bit programming (see figure 29, ?protection register map? on page 67 ). the user-programmable protection registers contain one-time programmable (otp) bits; when programmed, register bits cannot be erased. each protection register can be accessed multiple times to program individual bits, as long as the register remains unlocked. each protection register has an associated lock register bit. when a lock register bit is programmed, the associated protection register can only be read; it can no longer be programmed. additionally, because the lock register bits themselves are otp, when programmed, lock register bits cannot be erased. therefore, when a protection register is locked, it cannot be unlocked
november 2007 datasheet 251902-12 67 numonyx? strataflash ? wireless memory (l18) . 13.2.1 reading the protection registers the protection registers can be read from within any partition?s address space. to read the protection register, first issue the read device identifier command at any partitions? address to place that partition in the read device identifier state (see section 9.2, ?device commands? on page 44 ). next, perform a read operation at that partition?s base address plus the address offset corresponding to the register to be read. table 29, ?device identifier information? on page 74 shows the address offsets of the protection registers and lock registers. register data is read 16 bits at a time. note: if a program or erase operation occurs within the device while it is reading a protection register, certain restrictions may apply. see table 27, ?simultaneous operation restrictions? on page 72 for details. figure 29: protection register map 0x89 lock register 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x102 0x109 0x8a 0x91 128-bit protection register 16 (user-programmable) 128-bit protection register 1 (user-programmable) 0x88 0x85 64-bit segment (user-programmable) 0x84 0x81 0x80 lock register 0 64-bit segment (factory-programmed) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 128-bit protection register 0
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 68 251902-12 13.2.2 programming the protection registers to program any of the protection registers, first issue the program protection register command at the parameter partition?s base address plus the offset to the desired protection register (see section 9.2, ?device commands? on page 44 ). next, write the desired protection register data to the same protection register address (see figure 29, ?protection register map? on page 67 ). the device programs the 64-bit and 128-bit user-programmable protection register data 16 bits at a time (see figure 46, ?protection register programming flowchart? on page 90 ). issuing the program protection register command outside of the protection register?s address space causes a program error (sr[4] set). attempting to program a locked protection register causes a program error (sr[4] set) and a lock error (sr[1] set). note: if a program or erase operation occurs when programming a protection register, certain restrictions may apply. see table 27, ?simultaneous operation restrictions? on page 72 for details. 13.2.3 locking the protection registers each protection register can be locked by programming its respective lock bit in the lock register. to lock a protection register, program the corresponding bit in the lock register by issuing the program lock register command, followed by the desired lock register data (see section 9.2, ?device commands? on page 44 ). the physical addresses of the lock registers are 0x80 for register 0 and 0x89 for register 1. these addresses are used when programming the lock registers (see table 29, ?device identifier information? on page 74 ). bit 0 of lock register 0 is already programmed at the factory, locking the lower, pre- programmed 64-bit region of the first 128-bit protection register containing the unique identification number of the device. bit 1 of lock register 0 can be programmed by the user to lock the user-programmable, 64-bit region of the first 128-bit protection register. the other bits in lock register 0 are not used. lock register 1 controls the locking of the upper sixteen 128-bit protection registers. each of the 16 bits of lock register 1 correspond to each of the upper sixteen 128-bit protection registers. programming a bit in lock register 1 locks the corresponding 128-bit protection register. caution: after being locked, the protection registers cannot be unlocked.
november 2007 datasheet 251902-12 69 numonyx? strataflash ? wireless memory (l18) 14.0 dual-operation considerations the multi-partition architecture of the device allows background programming (or erasing) to occur in one partition while data reads (or code execution) take place in another partition. 14.1 memory partitioning the l18 flash memory array is divided into multiple 8-mbit partitions, which allows simultaneous read-while-write operations. simultaneous program and erase is not allowed. only one partition at a time can be in program or erase mode. the flash device supports read-while-write operations with bus cycle granularity and not command granularity. in other words, it is not assumed that both bus cycles of a two cycle command (an erase command for example) will always occur as back to back bus cycles to the flash device. in practice, code fetches (reads) may be interspersed between write cycles to the flash device, and they will likely be directed to a different partition than the one being written. this is especially true when a processor is executing code from one partition that instructs the processor to program or erase in another partition. 14.2 read-while-write command sequences when issuing commands to the device, a read operation can occur between 2-cycle write command?s ( figure 30 , and figure 31 ). however, a write operation issued between a 2-cycle commands write sequence causes a command sequence error. (see figure 32 ) when reading from the same partition after issuing a setup command, status register data is returned, regardless of the read mode of the partition prior to issuing the setup command. figure 30: operating mode with correct command sequence example partition a partition a partition b 0x20 0xd0 0xff a ddress [a] we# [w] oe# [g] data [d/q]
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 70 251902-12 14.2.1 simultaneous operation details the numonyx? strataflash ? wireless memory (l18) supports simultaneous read from one partition while programming or erasing in any other partition. certain features like the protection registers and query data have special requirements with respect to simultaneous operation capability. these will be detailed in the following sections. 14.2.2 synchronous and asynchronous rww characteristics and waveforms this section describes the transition of write operation to asynchronous read, write to synchronous read, and write operation with clock active. 14.2.2.1 write operation to asynchronous read transition w18 - t whav the ac parameter w18 (t whav -we# high to address valid) is required when transitioning from a write cycle (we# going high) to perform an asynchronous read (only address valid is required). 14.2.2.2 write to synchronous read operation transition w19 and w20 - t whcv and t whvh figure 31: operating mode with correct command sequence example figure 32: operating mode with illegal command sequence example partition a partition b partition a 0x20 valid array data 0xd0 a d d re ss [ a ] we# [w] oe# [g] data [d/q] partition a partition b partition a partition a 0x20 0xff 0xd0 sr[7:0] a ddress [a] we# [w] oe# [g] data [d/q]
november 2007 datasheet 251902-12 71 numonyx? strataflash ? wireless memory (l18) the ac parameters w19 or w20 (t whcv -we# high to clock valid, and t whvh - we# high to adv# high) is required when transitioning from a write cycle (we# going high) to perform a synchronous burst read. a delay from we# going high to a valid clock edge or adv# going high to latch a new address must be met. 14.2.2.3 write operation with clock active w21 - t vhwl w22 - t chwl the ac parameters w21 (t vhwl - adv# high to we# low) and w22 (t chwl -clock high to we# low) are required during write operations when the device is in a synchronous mode and the clock is active. a write bus cycle consists of two parts: ? the host provides an address to the flash device; and ? the host then provides data to the flash device. the flash device in turn binds the received data with the received address. when operating synchronously (rcr[15] = 0), the address of a write cycle may be provided to the flash by the first active clock edge with adv# low, or rising edge of adv# as long as the applicable cycle separation conditions are met between each cycle. if neither a clock edge nor a rising adv# edge is used to provide a new address at the beginning of a write cycle (the clock is stopped and adv# is low), the address may also be provided to the flash device by holding the address bus stable for the required amount of time (w5, t avwh ) before the rising we# edge. alternatively, the host may choose not to provide an address to the flash device during subsequent write cycles (if adv# is high and only ce# or we# is toggled to separate the prior cycle from the current write cycle). in this case, the flash device will use the most recently provided address from the host. refer to figure 20, ?write to asynchronous read timing? on page 37 , figure 21, ?synchronous read to write timing? on page 37 , and figure 22, ?write to synchronous read timing? on page 38 , for representation of these timings. 14.2.3 read operation during buffered programming the multi-partition architecture of the device allows background programming (or erasing) to occur in one partition while data reads (or code execution) take place in another partition. to perform a read while buffered programming operation, first issue a buffered program set up command in a partition. when a read operation occurs in the same partition after issuing a setup command, status register data will be returned, regardless of the read mode of the partition prior to issuing the setup command. to read data from a block in other partition and the other partition already in read array mode, a new block address must be issued. however, if the other partition is not already in read array mode, issuing a read array command will cause the buffered program operation to abort and a command sequence error would be posted in the status register. see figure 41, ?buffer program flowchart? on page 85 for more details. note: simultaneous read-while-buffered efp is not supported.
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 72 251902-12 14.3 simultaneous operation restrictions since the numonyx? strataflash ? wireless memory (l18) supports simultaneous read from one partition while programming or erasing in another partition, certain features like the protection registers and cfi query data have special requirements with respect to simultaneous operation capability. ( ta b l e 2 7 provides details on restrictions during simultaneous operations.) table 27: simultaneous operation restrictions protection register or cfi data parameter partition array data other partitions notes read (see notes) write/ erase while programming or erasing in a main partition, the protection register or cfi data may be read from any other partition. reading the parameter partition array data is not allowed if the protection register or query data is being read from addresses within the parameter partition. (see notes) read write/ erase while programming or erasing in a main partition, read operations are allowed in the parameter partition. accessing the protection registers or cfi data from parameter partition addresses is not allowed when reading array data from the parameter partition. read read write/ erase while programming or erasing in a main partition, read operations are allowed in the parameter partition. accessing the protection registers or cfi data in a partition that is different from the one being programed/erased, and also different from the parameter partition is allowed. write no access allowed read while programming the protection register, reads are only allowed in the other main partitions. access to array data in the parameter partition is not allowed. programming of the protection register can only occur in the parameter partition, which means this partition is in read status. no access allowed write/erase read while programming or erasing the parameter partition, reads of the protection registers or cfi data are not allowed in any partition. reads in partitions other than the parameter partition are supported.
november 2007 datasheet 251902-12 73 numonyx? strataflash ? wireless memory (l18) 15.0 special read states the following sections describe non-array read states. non-array reads can be performed in asynchronous read or synchronous burst mode. a non-array read operation occurs as asynchronous single-word mode. when non-array reads are performed in asynchronous page mode only the first data is valid and all subsequent data are undefined. when a non- array read operation occurs as synchronous burst mode, the same word of data requested will be output on successive clock edges until the burst length requirements are satisfied. each partition can be in one of its read states independent of other partitions? modes. see figure 11, ?asynchronous single-word read with adv# low? on page 31 and figure 14, ?synchronous single-word array or non-array read timing? on page 33 for details. 15.1 read status register the status of any partition is determined by reading the status register from the address of that particular partition. to read the status register, issue the read status register command within the desired partition?s address range. status register information is available at the partition address to which the read status register, word program, or block erase command was issued. status register data is automatically made available following a word program, block erase, or block lock command sequence. reads from a partition after any of these command sequences outputs that partition?s status until another valid command is written to that partition (e.g. read array command). the status register is read using single asynchronous-mode or synchronous burst mode reads. status register data is output on dq[7:0], while 0x00 is output on dq[15:8]. in asynchronous mode the falling edge of oe#, or ce# (whichever occurs first) updates and latches the status register contents. however, reading the status register in synchronous burst mode, ce# or adv# must be toggled to update status data. the status register read operations do not affect the read state of the other partitions. the device write status bit (sr[7]) provides overall status of the device. the partition status bit (sr[0]) indicates whether the addressed partition or some other partition is actively programming or erasing. status register bits sr[6:1] present status and error information about the program, erase, suspend, v pp , and block-locked operations. table 28: status register description (sheet 1 of 2) status register (sr) default value = 0x80 device write status erase suspend status erase status program status v pp status program suspend status block-locked status partition status dws ess es ps vpps pss bls pws 76543210 bit name description 7 device write status (dws) 0 = device is busy; program or erase cycle in progress; sr[0] valid. 1 = device is ready; sr[6:1] are valid. 6 erase suspend status (ess) 0 = erase suspend not in effect. 1 = erase suspend in effect. 5 erase status (es) 0 = erase successful. 1 = erase fail or program sequence error when set with sr[4,7].
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 74 251902-12 always clear the status register prior to resuming erase operations. this avoids status register ambiguity when issuing commands during erase suspend. if a command sequence error occurs during an erase-suspend state, the status register contains the command sequence error status (sr[7,5,4] set). when the erase operation resumes and finishes, possible errors during the erase operation cannot be detected via the status register because it contains the previous error status. 15.1.1 clear status register the clear status register command clears the status register, leaving all partition read states unchanged. it functions independent of v pp . the write state machine (wsm) sets and clears sr[7,6,2,0], but it sets bits sr[5:3,1] without clearing them. the status register should be cleared before starting a command sequence to avoid any ambiguity. a device reset also clears the status register. 15.2 read device identifier the read device identifier command instructs the addressed partition to output manufacturer code, device identifier code, block-lock status, protection register data, or configuration register data when that partition?s addresses are read (see section 9.2, ?device commands? on page 44 for details on issuing the read device identifier command). table 29, ?device identifier information? on page 74 and table 30, ?device id codes? on page 75 show the address offsets and data values for this device. issuing a read device identifier command to a partition that is programming or erasing places that partition in the read identifier state while the partition continues to program or erase in the background. 4program status (ps) 0 = program successful. 1 = program fail or program sequence error when set with sr[5,7] 3v pp status (vpps) 0 = vpp within acceptable limits during program or erase operation. 1 = vpp < vpplk during program or erase operation. 2 program suspend status (pss) 0 = program suspend not in effect. 1 = program suspend in effect. 1 block-locked status (bls) 0 = block not locked during program or erase. 1 = block locked during program or erase; operation aborted. 0 partition write status (pws) dws pws 0 0 = program or erase operation in addressed partition. 0 1 = program or erase operation in other partition. 1 0 = no active program or erase operations. 1 1 = reserved. (non-buffered efp operation. for buffered efp operation, see section 11.3, ?buffered enhanced factory programming? on page 58 ). table 28: status register description (sheet 2 of 2) status register (sr) default value = 0x80 table 29: device identifier information (sheet 1 of 2) item address (1,2) data manufacturer code pba + 0x00 0089h device id code pba + 0x01 id (see ta b l e 3 0 )
november 2007 datasheet 251902-12 75 numonyx? strataflash ? wireless memory (l18) 15.3 cfi query the cfi query command instructs the device to output common flash interface (cfi) data when partition addresses are read. see section 9.2, ?device commands? on page 44 for details on issuing the cfi query command. appendix c, ?common flash interface? on page 91 shows cfi information and address offsets within the cfi database. issuing the cfi query command to a partition that is programming or erasing places that partition?s outputs in the cfi query state, while the partition continues to program or erase in the background. the cfi query command is subject to read restrictions dependent on parameter partition availability, as described in ta b l e 2 7 . block lock configuration: bba + 0x02 lock bit: ? block is unlocked dq 0 = 0b0 ? block is locked dq 0 = 0b1 ? block is not locked-down dq 1 = 0b0 ? block is locked-down dq 1 = 0b1 configuration register pba + 0x05 configuration register data lock register 0 pba + 0x80 pr-lk0 64-bit factory-programmed protection register pba + 0x81?0x84 factory protection register data 64-bit user-programmable protection register pba + 0x85?0x88 user protection register data lock register 1 pba + 0x89 protection register data 16x128-bit user-programmable protection registers pba + 0x8a?0x109 pr-lk1 notes: 1. pba = partition base address. 2. bba = block base address. table 29: device identifier information (sheet 2 of 2) item address (1,2) data table 30: device id codes id code type device density device identifier codes ?t (top parameter) ?b (bottom parameter) device code 128 mbit 880c 880f 256 mbit 880d 8810
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 76 251902-12 appendix a write state machine (wsm) figure 33 through figure 38 show the command state transitions (next state table) based on incoming commands. only one partition can be actively programming or erasing at a time. each partition stays in its last read state (read array, read device id, cfi query or read status register) until a new command changes it. the next wsm state does not depend on the partition?s output state. figure 33: write state machine?next state table (sheet 1 of 6) read array (2) word program (3,4) buffered program (bp) erase setup (3,4) buffered enhanced factory pgm setup (3, 4) be confirm, p/e resume, ulb, confirm (8) bp / prg / erase suspend read status clear status register (5) read id/query lock, unlock, lock-down, cr setup (4) (ffh) (10h/40h) (e8h) (20h) (80h) (d0h) (b0h) (70h) (50h) (90h, 98h) (60h) ready program setup bp setup erase setup befp setup lock/cr setup ready (unlock block) setup busy setup busy word program suspend suspend word program busy setup bp load 1 bp load 2 bp confirm bp busy bp busy bp suspend bp suspend bp busy setup erase busy busy erase suspend suspend erase suspend word program setup in erase suspend bp setup in erase suspend erase busy lock/cr setup in erase suspend bp suspend erase bp busy erase busy erase suspend erase suspend ready (error) erase busy bp suspend ready (error) word program program busy word program suspend word program busy otp ready (lock error) ready ready ready (lock error) otp busy current chip state (7) command input to chip and resulting chip next state bp bp busy lock/cr setup bp load 2 ready (error) ready (error) word program busy bp confirm if data load into program buffer is complete; else bp load 2 word program suspend bp load 1
november 2007 datasheet 251902-12 77 numonyx? strataflash ? wireless memory (l18) figure 34: write state machine?next state table (sheet 2 of 6) setup busy word program suspend in erase suspend suspend word program busy in erase suspend setup bp load 1 bp load 2 bp confirm bp busy in erase suspend bp busy bp suspend in erase suspend bp suspend bp busy in erase suspend erase suspend (unlock block) setup befp loading data (x=32) erase suspend (error) erase suspend (lock error [botch]) ready (error) ready (error) bp suspend in erase suspend ready (error in erase suspend) bp busy in erase suspend bp suspend in erase suspend bp busy in erase suspend word program busy in erase suspend word program in erase suspend word program busy in erase suspend word program suspend in erase suspend lock/cr setup in erase suspend erase suspend (lock error) bp confirm if data load into program buffer is complete; else bp load 2 bp in erase suspend bp load 2 word program busy in erase suspend busy word program suspend in erase suspend befp program and verify busy (if block address given matches address given on befp setup command). commands treated as data. ( 7) befp busy buffered enhanced factory program mode bp load 1 read array ( 2 ) word program (3,4) buffered program (bp) erase setup (3,4) buffered enhanced factory pgm setup (3, 4) be confirm, p/e resume, ulb, confirm (8) bp / prg / erase suspend read status clear status register (5) read id/query lock, unlock, lock-down, cr setup (4) (ffh) (10h/40h) (e8h) (20h) (80h) (d0h) (b0h) (70h) (50h) (90h, 98h) (60h) current chip state (7) command input to chip and resulting chip next state
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 78 251902-12 figure 35: write state machine?next state table (sheet 3 of 6) setup busy setup busy suspend setup bp load 1 bp load 2 bp confirm bp busy bp suspend setup busy suspend erase word program otp ready current chip state (7) bp lock/cr setup otp setup (4) lock block confirm (8) lock-down block confirm (8) write rcr confirm (8) block address (?wa0) 9 illegal cmds or befp data (1) (c0h) (01h) (2fh) (03h) (xxxxh) (all other codes) otp setup ready (lock error) ready (lock block) ready (lock down blk) ready (set cr) ready n/a ready ready (bp load 2 bp load 2 ready bp confirm if data load into program buffer is complete; else bp load 2 ready (error) (proceed if unlocked or lock error) ready (error) ready ready n/a bp confirm if data load into program buffer is complete; else bp load 2 ready (error) bp busy erase busy word program suspend bp load 1 bp load 2 otp busy word program busy word program busy wsm operation completes command input to chip and resultin g chip next state n/a ready (lock error) ready bp suspend ready (error) erase suspend n/a n/a
november 2007 datasheet 251902-12 79 numonyx? strataflash ? wireless memory (l18) figure 36: write state machine?next state table (sheet 4 of 6) otp setup (4) lock block confirm (8) lock-down block confirm (8) write rcr confirm (8) block address (?wa0) 9 illegal cmds or befp data (1) (c0h) (01h) (2fh) (03h) (xxxxh) (all other codes) wsm operation completes command input to chip and resulting chip next state current chip state (7) na erase suspend n/a ready (bp load 2 bp load 2 ready bp confirm if data load into program buffer is complete; else bp load 2 ready (error) (proceed if unlocked or lock error) ready (error) erase suspend erase suspend (lock error) erase suspend (lock block) erase suspend (lock down block) erase suspend (set cr) ready (befp loading data) ready (error) befp program and verify busy (if block address given matches address given on befp setup command). commands treated as data. (7) bp load 1 ready (error) bp confirm if data load into program buffer is complete; else bp load 2 ready (error in erase suspend) word program suspend in erase suspend bp load 2 ready word program busy in erase suspend busy word program busy in erase suspend befp busy ready erase suspend (lock error) n/a bp busy in erase suspend bp suspend in erase suspend n/a setup busy suspend setup bp load 1 bp load 2 bp confirm bp busy bp suspend setup befp busy buffered enhanced factory program mode lock/cr setup in erase suspend bp in erase suspend word program in erase suspend
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 80 251902-12 figure 37: write state machine?next state table (sheet 5 of 6) read array ( 2 ) word program setup (3,4) bp setup erase setup (3,4) buffered enhanced factory pgm setup (3, 4) be confirm, p/e resume, ulb confirm (8) program/ erase suspend read status clear status register (5) read id/query lock, unlock, lock-down, cr setup (4) (ffh) (10h/40h) (e8h) (20h) (30h) (d0h) (b0h) (70h) (50h) (90h, 98h) (60h) status read command input to chip and resulting output mux next state output next state table status read output mux does not change. status read id read status read ready, erase suspend, bp suspend status read lock/cr setup, lock/cr setup in erase susp output does not change. status read befp setup, befp pgm & verify busy, erase setup, otp setup, bp: setup , load 1, load 2, confirm, word pgm setup, word pgm setup in erase susp, bp setup, load1, load 2, confirm in erase suspend current chip state otp busy bp busy, word program busy, erase busy, bp busy bp busy in erase suspend word pgm suspend, word pgm busy in erase suspend, pgm suspend in erase sus p end read array
november 2007 datasheet 251902-12 81 numonyx? strataflash ? wireless memory (l18) notes: 1. "illegal commands" include commands outside of the allowed command set (allowed commands: 40h [pgm], 20h [erase], etc.) 2. if a "read array" is attempted from a busy partition, the result will be invalid data. the id and query data are located at different locations in the address map. 3. 1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or unexpected results will occur. 4. to protect memory contents against erroneous command sequences, there are specific instances in a multi-cycle command sequence in which the second cycle will be ignored. for example, when the device is program suspended and an erase setup command (0x20) is given followed by a confirm/resume command (0xd0), the second command will be ignored because it is unclear whether the user intends to erase the block or resume the program operation. 5. the clear status command only clears the error bits in the status register if the device is not in the following modes: wsm running (pgm busy, erase busy, pgm busy in erase suspend, otp busy, befp modes). figure 38: write state machine?next state table (sheet 6 of 6) otp busy bp busy, word program busy, erase busy, bp busy bp busy in erase suspend word pgm suspend, word pgm busy in erase suspend, pgm suspend in erase sus p end befp setup, befp pgm & verify busy, erase setup, otp setup, bp: setup , load 1, load 2, confirm, word pgm setup, word pgm setup in erase susp, bp setup, load1, load 2, confirm in erase suspend current chip state ready, erase suspend, bp suspend lock/cr setup, lock/cr setup in erase susp otp setup (4) lock block confirm (8) lock-down block confirm (8) write cr confirm (8) block address (?wa0) illegal cmds or befp data (1) (c0h) (01h) (2fh) (03h) (ffffh) (all other codes) wsm operation completes output does not change. a rray read status read array read output does not change. output does not change. status read status read status read command input to chip and resulting output mux next state output next state table
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 82 251902-12 6. befp writes are only allowed when the status register bit #0 = 0, or else the data is ignored. 7. the "current state" is that of the "chip" and not of the "partition"; each partition "remembers" which output (array, id/cfi or status) it was last pointed to on the last instruction to the "chip", but the next state of the chip does not depend on where the partition's output mux is presently pointing to. 8. confirm commands (lock block, unlock block, lock-down block, configuration register) perform the operation and then move to the ready state. 9. wa0 refers to the block address latched during the first write cycle of the current operation.
november 2007 datasheet 251902-12 83 numonyx? strataflash ? wireless memory (l18) appendix b flowcharts figure 39: word program flowchart program suspend loop start write 0x40, word address write data, word address read status register sr[7] = full status check (if desired) program complete suspend? 1 0 no yes word program procedure repeat for subsequent word program operations. full status register check can be done after each program, or after a sequence of program operations. write 0xff after the last operation to set to the read array state. comments bus operation command data = 0x40 addr = location to program write program setup data = data to program addr = location to program write data status register data read none check sr[7] 1 = wsm ready 0 = wsm busy idle none (setup) (confirm) full status check procedure read status register program successful sr[3] = sr[1] = 0 0 sr[4] = 0 1 1 1 v pp range error device protect error program error if an error is detected, clear the status register before continuing operations - only the clear staus register command clears the status register error bits. idle idle bus operation none none command check sr[3]: 1 = v pp error check sr[4]: 1 = data program error comments idle none check sr[1]: 1 = block locked; operation aborted
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 84 251902-12 figure 40: program suspend/resume flowchart read status register sr.7 = sr.2 = write ffh susp partition read array data program completed done reading write ffh pgm' d partition write d0h any addr ess program resumed read array data 0 no 0 yes 1 1 program suspend / resume procedure wr i te program resume data = d0h addr = suspended block (ba) bus operation command comments wr i te program suspend data = b0h addr = block to suspend (ba) standby check sr.7 1 = wsm r eady 0 = wsm busy standby check sr.2 1 = program suspended 0 = pr ogr am com pl eted wr i te read array data = ffh addr = any address within the suspended par titi on read read array data from block other than the one being programmed read status r egi ster data addr = suspended block (ba) pgm_sus.wmf start write b0h any addr ess program suspend read status program resume read array read array wr i te 70h same partition wr i te read status data = 70h addr = same partition if t he suspended part it ion was placed in r ead array mode: wr i te read status return partition to status mode: data = 70h addr = same partition wr i te 70h same partition read status
november 2007 datasheet 251902-12 85 numonyx? strataflash ? wireless memory (l18) figure 41: buffer program flowchart buffer programming procedure start get next target address issue buffer prog. cmd. 0xe8, word address read status register at word address wr i te buf fer available? sr[7] = 1 = yes device supports buffer writes? set timeout or loop counter timeout or count expired? write confirm 0xd0 and word address (note 5) yes no buffer program data, start word address x = 0 0 = no yes use single word programming abort buffer program? no x = n? write buffer data, word address x = x + 1 write to another block address buffer program aborted no yes yes write word count, word address suspend program loop read status register (note 7) is bp finished? sr[7] = full status check if desired program complete suspend program? 1=yes 0=no yes no issue read status register command no 1. word count value on d[7:0] is loaded into the word count register. count ranges for this device are n = 0x00 to 0x1f. 2. the device outputs the status register when read. 3. write buffer contents will be programmed at the issued word address. 4. align the start address on a write buffer boundary for maximum programming performance (i.e., a[4:0] of the start word address = 0x00). 5. the buffered programming confirm command must be issued to an address in the same block, for example, the original start word address, or the last address used during the loop that loaded the buffer data. 6. the status register indicates an improper command sequence if the buffer program command is aborted; use the clear status register command to clear error bits. 7. the status register can be read from any addresses within the programming partition. full status check can be done after all erase and write sequences complete. write 0xff after the last operation to place the partition in the read array state. bus operation idle read command none none write buffer prog. setup read none idle none comments check sr[7]: 1 = wsm ready 0 = wsm busy status register data addr = note 7 data = 0xe8 addr = word address sr[7] = valid addr = word address check sr[7]: 1 = write buffer available 0 = no write buffer available write (notes 5, 6) buffer prog. conf. data = 0xd0 addr = original word address write (notes 1, 2) none data = n-1 = word count n = 0 corresponds to count = 1 addr = word address write (notes 3, 4) none data = write buffer data addr = start word address write (note 3) none data = write buffer data addr = word address other partitions of the device can be read by addressing those partitions and driving oe# low. (any write commands are not allowed during this period.) 0xff commands can be issued to read from any blocks in other partitions
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 86 251902-12 figure 42: buffered efp flowchart write data @ 1 st word address last data? write 0xffff, address not within current block program done? read status reg. y no (sr[7]=0) full status check procedure program complete read status reg. befp exited? yes (sr[7]=1) start write 0x80 @ 1 st word address v pp applied, block unlocked write 0xd0 @ 1 st word address befp setup done? read status reg. exit n program & verify phase exit phase setup phase buffered enhanced factory programming (buffered-efp) procedure x = 32? initialize count: x = 0 increment count: x = x+1 y notes: 1. first-word address to be programmed within the target block must be aligned on a write-buffer boundary. 2. write-buffer contents are programmed sequentially to the flash array starting at the first word address; wsm internally increments addressing. n check v pp , lock errors (sr[3,1]) yes (sr[7]=0) comments bus state operation befp setup delay data stream ready? read status reg. no (sr[0]=1) repeat for subsequent blocks; after befp exit, a full status register check can determine if any program error occurred; see full status register check procedure in the word program flowchart. write 0xff to enter read array state. check sr[7]: 0 = exit not completed 1 = exit completed check exit status read status register data = status reg. data address = 1st word addr befp exit standby if sr[7] is set, check: sr[3] set = v pp error sr[1] set = locked block error condition check standby check sr[7]: 0 = befp ready 1 = befp not ready befp setup done? standby data = status reg. data address = 1 st word addr status register read data = 0xd0 @ 1 st word address befp confirm write data = 0x80 @ 1 st word address befp setup write (note 1) v pph applied to vpp unlock block write befp setup bus state comments operation no (sr[0]=1) yes (sr[0]=0) no (sr[7]=1) yes (sr[0]=0) befp program & verify comments bus state operation write (note 2) load buffer standby increment count standby initialize count data = data to program address = 1 st word addr. x = x+1 x = 0 standby buffer full? x = 32? yes = read sr[0] no = load next data word read standby status register data stream ready? data = status register data address = 1 st word addr. check sr[0]: 0 = ready for data 1 = not ready for data read standby standby write status register program done? last data? exit prog & verify phase data = status reg. data address = 1 st word addr. check sr[0]: 0 = program done 1 = program in progress no = fill buffer again yes = exit data = 0xffff @ address not in current block
november 2007 datasheet 251902-12 87 numonyx? strataflash ? wireless memory (l18) figure 43: block erase flowchart start full erase status check procedure repeat for subsequent block erasures. full status register check can be done after each block erase or after a sequence of block erasures. write 0xff after the last operation to enter read array mode. only the clear status register command clears sr[1, 3, 4, 5]. if an error is detected, clear the status register before attempting an erase retry or other error recovery. no suspend erase 1 0 0 0 1 1,1 1 1 0 yes suspend erase loop 0 write 0x20, block address write 0xd0, block address read status register sr[7] = full erase status check (if desired) block erase complete read status register block erase successful sr[1] = block locked error block erase procedure bus operation command comments write block erase setup data = 0x20 addr = block to be erased (ba) write erase confirm data = 0xd0 addr = block to be erased (ba) read none status register data. idle none check sr[7]: 1 = wsm ready 0 = wsm busy bus operation command comments sr[3] = v pp range error sr[4,5] = command sequence error sr[5] = block erase error idle none check sr[3]: 1 = v pp range error idle none check sr[4,5]: both 1 = command sequence error idle none check sr[5]: 1 = block erase error idle none check sr[1]: 1 = attempted erase of locked block; erase aborted. (block erase) (erase confirm)
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 88 251902-12 figure 44: erase suspend/resume flowchart er ase completed read ar r ay data 0 0 no read 1 program program loop read ar ray data 1 start read status regi ster sr[7] = sr[6] = er ase resumed read or program? done wr i te wr i te idle idle wr i te er ase suspend read ar r ay or pr ogr am none none pr ogr am resume data = 0xb0 addr = same par ti tion addr ess as above data = 0xff or 0x40 addr = any addr ess wi thin the suspended par ti tion check sr[7]: 1 = wsm r eady 0 = wsm busy check sr[6]: 1 = er ase suspended 0 = erase completed data = 0xd0 addr = any addr ess bus operation command comments read none status register data. addr = same par ti tion read or wr i te none read ar r ay or pr ogr am data fr om/to bl ock other than the one being er ased erase suspend / resume procedure if t he suspended part it ion was placed in read array mode or a program loop: wr ite 0xb0, any addr ess (e ra se susp end ) wr ite 0x70, sam e partition (read status) wr ite 0xd0, any addr ess (erase resume) wr ite 0x70, sam e partition (read status) wr ite 0xff, erased partition (read array) wr i te read status data = 0x70 addr = any parti ti on addr ess wr i te read status register retur n par ti tion to status m ode: data = 0x70 addr = same par ti tion
november 2007 datasheet 251902-12 89 numonyx? strataflash ? wireless memory (l18) figure 45: block lock operations flowchart no start write 0x60, block address write 0x90 read block lock status locking change? lock change complete write either 0x01/0xd0/0x2f, block address write 0xff partition address yes write write write (optional) read (optional) idle write lock setup lock, unlock, or lock-down confirm read device id block lock status none read array data = 0x60 addr = block to lock/unlock/lock-down data = 0x01 (block lock) 0xd0 (block unlock) 0x2f (lock-down block) addr = block to lock/unlock/lock-down data = 0x90 addr = block address + offset 2 block lock status data addr = block address + offset 2 confirm locking change on d[1,0]. data = 0xff addr = block address bus operation command comments locking operations procedure (lock confirm) (read device id) (read array) optional (lock setup)
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 90 251902-12 figure 46: protection register programming flowchart full status check procedure program protection register operation addresses must be within the protection register address space. addresses outside this space will return an error. repeat for subsequent programming operations. full status register check can be done after each program, or after a sequence of program operations. write 0xff after the last operation to set read array state. only the clear staus register command clears sr[1, 3, 4]. if an error is detected, clear the status register before attempting a program retry or other error recovery. 1 0 1 1 1 protection register programming procedure start write 0xc0, pr address write pr address & data read status register sr[7] = full status check (if desired) program complete read status register data program successful sr[3] = sr[4] = sr[1] = v pp range error program error register locked; program aborted idle idle bus operation none none command check sr[3]: 1 =v pp range error check sr[4]: 1 =programming error comments write write idle program pr setup protection program none data = 0xc0 addr = first location to program data = data to program addr = location to program check sr[7]: 1 = wsm ready 0 = wsm busy bus operation command comments read none status register data. idle none check sr[1]: 1 =block locked; operation aborted (program setup) (confirm data) 0 0 0
november 2007 datasheet 251902-12 91 numonyx? strataflash ? wireless memory (l18) appendix c common flash interface the common flash interface (cfi) is part of an overall specification for multiple command-set and control-interface descriptions. this appendix describes the database structure containing the data returned by a read operation after issuing the cfi query command (see section 9.2, ?device commands? on page 44 ). system software can parse this database structure to obtain information about the flash device, such as block size, density, bus width, and electrical specifications. the system software will then know which command set(s) to use to properly perform flash writes, block erases, reads and otherwise control the flash device. c.1 query structure output the query database allows system software to obtain information for controlling the flash device. this section describes the device?s cfi-compliant interface that allows access to query data. query data are presented on the lowest-order data outputs (dq 7-0 ) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the query table device starting address is a 10h, which is a word address for x16 devices. for a word-wide (x16) device, the first two query-structure bytes, ascii ?q? and ?r,? appear on the low byte at word addresses 10h and 11h. this cfi-compliant device outputs 00h data on upper bytes. the device outputs ascii ?q? in the low byte (dq 7-0 ) and 00h in the high byte (dq 15-8 ). at query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. in all of the following tables, addresses and data are represented in hexadecimal notation, so the ?h? suffix has been dropped. in addition, since the upper byte of word- wide devices is always ?00h,? the leading ?00? has been dropped from the table notation and only the lower byte value is shown. any x16 device outputs can be assumed to have 00h on the upper byte in this mode. table 31: summary of query structure output as a function of device and mode device hex offset hex code ascii value device addresses 00010: 51 ?q? 00011: 52 ?r? 00012: 59 ?y?
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 92 251902-12 table 32: example of query structure output of x16- devices c.2 query structure overview the query command causes the flash component to display the common flash interface (cfi) query structure or ?database.? the structure sub-sections and address locations are summarized in ta b l e 3 3 . table 33: query structure notes: 1. refer to the query structure output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. ba = block address beginning location (i.e., 08000h is block 1?s beginning location when the block size is 16-kword). 3. offset 15 defines ?p? which points to the primary numonyx-specific extended query table. c.3 cfi query identification string the identification string provides verification that the component supports the common flash interface specification. it also indicates the specification version and supported vendor-specified command set(s). table 34: cfi identification word addressin g : b y te addressin g : offset hex code value offset hex code value a x ?a 0 d 15 ? d 0 a x ?a 0 d 7 ? d 0 00010h 0051 "q" 00010h 51 "q" 00011h 0052 "r" 00011h 52 "r" 00012h 0059 "y" 00012h 59 "y" 00013h p_id lo prvendor 00013h p_id lo prvendor 00014h p_id hi id # 00014h p_id lo id # 00015h p lo prvendor 00015h p_id hi id # 00016h p hi tbladr 00016h ... ... 00017h a _id lo altvendor 00017h 00018h a _id hi id # 00018h ... ... ... ... offset sub-section name descri p tion (1) 00001-fh reserved reserved for vendor-specific information 00010h cfi query identification string command set id and vendor data offset 0001bh system interface information device timing & voltage information 00027h device geometry definition flash device layout p (3) primar y intel-specific extended quer y table vendor-defined additional information specific offset length description add. hex code value 10h 3 query-unique ascii string ?qry? 10: --51 "q" 11: --52 "r" 12: --59 "y" 13h 2 primary vendor command set and control interface id code. 13: --01 16-bit id code for vendor-s p ecified al g orithms 14: --00 15h 2 extended query table primary algorithm address 15: --0a 16: --01 17h 2 alternate vendor command set and control interface id code. 17: --00 0000h means no second vendor-specified algorithm exists 18: --00 19h 2 secondary algorithm extended query table address. 19: --00 0000h means none exists 1a: --00
november 2007 datasheet 251902-12 93 numonyx? strataflash ? wireless memory (l18) table 35: system interface information offset length description add. hex code value 1bh 1 1b: --17 1.7v 1ch 1 1c: --20 2.0v 1dh 1 1d: --85 8.5v 1eh 1 1e: --95 9.5v 1fh 1 ?n? such that t yp ical sin g le word p ro g ram time-out = 2 n s 20h 1 ?n? such that t yp ical max. buffer write time-out = 2 n s 21h 1 ?n? such that t yp ical block erase time-out = 2 n m-sec 21: --0a 1s 22h 1 ?n? such that t yp ical full chi p erase time-out = 2 n m-sec 22: --00 na 23h 1 ?n? such that maximum word p ro g ram time-out = 2 n times t yp ical 23: --01 512 s 24h 1 ?n? such that maximum buffer write time-out = 2 n times t yp ical 24: --01 1024 s 25h 1 ?n? such that maximum block erase time-out = 2 n times t yp ical 25: --02 4s 26h 1 ?n? such that maximum chi p erase time-out = 2 n times t yp ical 26: --00 na v pp [programming] supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts v pp [programming] supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts v cc logic supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts v cc logic supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 94 251902-12 c.4 device geometry definition table 36: device geometry definition offset len g th description code 27h 1 ?n? such that device size = 2 n in number of bytes 27: see table below 76543210 28h 2 ? ? ? ? x64 x32 x16 x8 28: --01 x16 15 14 13 12 11 10 9 8 ????????29:--00 2ah 2 ?n? such that maximum number of bytes in write buffer = 2 n 2a: --06 64 2b: --00 2ch 1 2c: 2dh 4 erase block region 1 information 2d: bits 0?15 = y, y+1 = number of identical-size erase blocks 2e: bits 16?31 = z, region erase block(s) size are z x 256 bytes 2f: 30: 31h 4 erase block region 2 information 31: bits 0?15 = y, y+1 = number of identical-size erase blocks 32: bits 16?31 = z, region erase block(s) size are z x 256 bytes 33: 34: 35h 4 reserved for future erase block region information 35: 36: 37: 38: see table below see table below see table below see table below flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table: number of erase block regions (x) within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device regions with one or more contiguous same-size erase blocks. 3. symmetrically blocked partitions have one blocking region address 64 mbit ?b ?t ?b ?t ?b ?t 27: --17 --17 --18 --18 --19 --19 28: --01 --01 --01 --01 --01 --01 29: --00 --00 --00 --00 --00 --00 2a: --06 --06 --06 --06 --06 --06 2b: --00 --00 --00 --00 --00 --00 2c: --02 --02 --02 --02 --02 --02 2d: --03 --3e --03 --7e --03 --fe 2e: --00 --00 --00 --00 --00 --00 2f: --80 --00 --80 --00 --80 --00 30: --00 --02 --00 --02 --00 --02 31: --3e --03 --7e --03 --fe --03 32: --00 --00 --00 --00 --00 --00 33: --00 --80 --00 --80 --00 --80 34: --02 --00 --02 --00 --02 --00 35: --00 --00 --00 --00 --00 --00 36: --00 --00 --00 --00 --00 --00 37: --00 --00 --00 --00 --00 --00 38: --00 --00 --00 --00 --00 --00 128 mbit 256 mbit
november 2007 datasheet 251902-12 95 numonyx? strataflash ? wireless memory (l18) c.5 numonyx-specific extended query table table 37: primary vendor-specific extended query offset (1) len g th description hex p = 10ah (optional flash features and commands) a dd. code v alue (p+0)h 3 primary extended query table 10a --50 "p" (p+1)h unique ascii string ?pri? 10b: --52 "r" (p+2)h 10c: --49 "i" (p+3)h 1 major version number, ascii 10d: --31 "1" (p+4)h 1 minor version number, ascii 10e: --33 "3" (p+5)h 4 optional feature and command support (1=yes, 0=no) 10f: --e6 (p+6)h bits 10?31 are reserved; undefined bits are ?0.? if bit 31 is 110: --03 (p+7)h ?1? then another 31 bit field of optional features follows at 111: --00 (p+8)h the end of the bit?30 field. 112: --00 bit 0 chip erase supported bit 0 = 0 no bit 1 suspend erase supported bit 1 = 1 yes bit 2 suspend program supported bit 2 = 1 yes bit 3 legacy lock/unlock supported bit 3 = 0 no bit 4 queued erase supported bit 4 = 0 no bit 5 instant individual block locking supported bit 5 = 1 yes bit 6 protection bits supported bit 6 = 1 yes bit 7 pagemode read supported bit 7 = 1 yes bit 8 synchronous read supported bit 8 = 1 yes bit 9 simultaneous operations supported bit 9 = 1 yes (p+9)h 1 113: --01 bit 0 pro g ram supported after erase suspend bit 0 = 1 yes (p+a)h 2 block status register mask 114: --03 (p+b)h bits 2?15 are reserved; undefined bits are ?0? 115: --00 bit 0 block lock-bit status register active bit 0 = 1 yes bit 1 block lock-down bit status active bit 1 = 1 yes (p+c)h 1 116: --18 1.8v (p+d)h 1 117: --90 9.0v supported functions after suspend: read array, status, query other supported operations are: bits 1?7 reserved; undefined bits are ?0? v cc logic supply highest performance program/erase voltage bits 0?3 bcd value in 100 mv bits 4?7 bcd value in volts v pp optimum program/erase supply voltage bits 0?3 bcd value in 100 mv bits 4?7 hex value in volts
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 96 251902-12 table 38: protection register information table 39: burst read information offset (1) len g th description hex p = 10ah (optional flash features and commands) a dd. code v alue (p+e)h 1 118: --02 2 (p+f)h 4 protection field 1: protection description 119: --80 80h (p+10)h this field describes user-available one time programmable 11a: --00 00h (p+11)h ( otp ) protection re g ister b y tes. some are pre-pro g rammed 11b: --03 8 byte (p+12)h 11c: --03 8 byte (p+13)h 10 protection field 2: protection description 11d: --89 89h (p+14)h 11e: --00 00h (p+15)h 11f: --00 00h (p+16)h 120: --00 00h (p+17)h 121: --00 0 (p+18)h bits 40?47 = ?n? n = factory pgm'd groups (high byte) 122: --00 0 (p+19)h 123: --00 0 (p+1a)h 124: --10 16 (p+1b)h 125: --00 0 (p+1c)h 126: --04 16 bits 48?55 = ?n? \ 2n = factory programmable bytes/group bits 56?63 = ?n? n = user pgm'd groups (low byte) bits 64?71 = ?n? n = user pg m'd g rou p s ( hi g h b y te ) bits 72?79 = ?n? 2 n = user programmable bytes/group with device-unique serial numbers. others are user programmable. bits 0?15 point to the protection register lock byte, the section?s first byte. the following bytes are factory pre-programmed and user-programmable. bits 0?7 = lock/bytes jedec-plane physical low address bits 8?15 = lock/bytes jedec-plane physical high address bits 16?23 = ?n? such that 2 n = factory pre-programmed bytes bits 24?31 = ?n? such that 2 n = user programmable bytes bits 0?31 point to the protection register physical lock-word address in the jedec-plane. following bytes are factory or user-programmable. bits 32?39 = ?n? n = factory pgm'd groups (low byte) number of protection register fields in jedec id space. ?00h,? indicates that 256 protection fields are available offset (1) len g th description hex p = 10ah (optional flash features and commands) a dd. code v alue (p+1d)h 1 127: --03 8 byte (p+1e)h 1 128: --04 4 (p+1f)h 1 129: --01 4 (p+20)h 1 synchronous mode read capability configuration 2 12a: --02 8 (p+21)h 1 synchronous mode read capability configuration 3 12b: --03 16 (p+22)h 1 synchronous mode read capability configuration 4 12c: --07 cont page mode read capability bits 0?7 = ?n? such that 2 n hex value represents the number of read-page bytes. see offset 28h for device word width to determine page-mode data output width. 00h indicates no read p a g e buffer. number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. synchronous mode read capability configuration 1 bits 3?7 = reserved bits 0?2 ?n? such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device?s burstable address space. this field?s 3-bit value can be written directly to the read configuration register bits 0?2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data out p ut width.
november 2007 datasheet 251902-12 97 numonyx? strataflash ? wireless memory (l18) table 40: partition and erase-block region information offset (1) see table below p= 10ah description a ddress bottom to p ( o p tional flash features and commands ) len bot top (p+23)h (p+23)h 1 12d: 12d: number of device hardware-partition regions within the device. x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions.
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 98 251902-12 table 41: partition region 1 information offset (1) see table below p = 10ah descri p tion a ddress bottom to p ( o p tional flash features and commands ) len bot top (p+24)h (p+24)h number of identical partitions within the partition region 2 12e: 12e: (p+25)h (p+25)h 12f: 12f: (p+26)h (p+26)h 1 130: 130: (p+27)h (p+27)h 1 131: 131: (p+28)h (p+28)h 1 132: 132: (p+29)h (p+29)h 1 133: 133: (p+2a)h (p+2a)h partition region 1 erase block type 1 information 4 134: 134: (p+2b)h (p+2b)h bits 0?15 = y, y+1 = number of identical-size erase blocks 135: 135: (p+2c)h (p+2c)h bits 16?31 = z, region erase block(s) size are z x 256 bytes 136: 136: (p+2d)h (p+2d)h 137: 137: (p+2e)h (p+2e)h partition 1 (erase block type 1) 2 138: 138: (p+2f)h (p+2f)h minimum block erase cycles x 1000 139: 139: (p+30)h (p+30)h 1 13a: 13a: (p+31)h (p+31)h 1 13b: 13b: (p+32)h partition region 1 erase block type 2 information 4 13c: (p+33)h bits 0?15 = y, y+1 = number of identical-size erase blocks 13d: (p+34)h bits 16?31 = z, region erase block(s) size are z x 256 bytes 13e: (p+35)h (bottom parameter device only) 13f: (p+36)h partition 1 (erase block type 2) 2 140: (p+37)h minimum block erase cycles x 1000 141: (p+38)h 1 142: (p+39)h 1 143: partition 1 (erase block type 1) bits per cell; internal ecc bits 0?3 = bits per cell in erase region bit 4 = reserved for ?internal ecc used? (1=yes, 0=no) bits 5?7 = reserve for future use partition 1 (erase block type 1) page mode and synchronous mode capabilities defined in table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3?7 = reserved for future use partition 1 (erase block type 2) bits per cell bits 0?3 = bits per cell in erase region bit 4 = reserved for ?internal ecc used? (1=yes, 0=no) bits 5?7 = reserve for future use partition 1 (erase block type 2) pagemode and synchronous mode capabilities defined in table 10 bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3?7 = reserved for future use number of program or erase operations allowed in a partition bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations simultaneous program or erase operations allowed in other partitions while a partition in this region is in program mode bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations simultaneous program or erase operations allowed in other partitions while a partition in this region is in erase mode bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations types of erase block regions in this partition region. x = 0 = no erase blocking; the partition region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. symmetrically blocked partitions have one blocking region. partition size = (type 1 blocks)x(type 1 block sizes) + (type 2 blocks)x(type 2 block sizes) +?+ (type n blocks)x(type n block sizes)
november 2007 datasheet 251902-12 99 numonyx? strataflash ? wireless memory (l18) table 42: partition region 2 information offset (1) see table below p = 10ah description a ddress bottom top ( optional flash features and commands ) len bot top (p+3a)h (p+32)h number of identical partitions within the partition region 2 144: 13c: (p+3b)h (p+33)h 145: 13d: (p+3c)h (p+34)h 1 146: 13e: (p+3d)h (p+35)h 1 147: 13f: (p+3e)h (p+36)h 1 148: 140: (p+3f)h (p+37)h 1 149: 141: (p+40)h (p+38)h partition region 2 erase block type 1 information 4 14a: 142: (p+41)h (p+39)h bits 0?15 = y, y+1 = number of identical-size erase blocks 14b: 143: (p+42)h (p+3a)h bits 16?31 = z, region erase block(s) size are z x 256 bytes 14c: 144: (p+43)h (p+3b)h 14d: 145: (p+44)h (p+3c)h partition 2 ( erase block t y pe 1 ) 2 14e: 146: (p+45)h (p+3d)h minimum bl ock erase cycles x 1000 14f: 147: (p+46)h (p+3e)h 1 150: 148: (p+47)h (p+3f)h 1 151: 149: (p+40)h partition region 2 erase block type 2 information 4 14a: (p+41)h bits 0?15 = y, y+1 = number of identical-size erase blocks 14b: (p+42)h bits 16?31 = z, region erase block(s) size are z x 256 bytes 14c: (p+43)h 14d: (p+44)h partition 2 ( erase block t y pe 2 ) 2 14e: (p+45)h minimum block erase cycles x 1000 14f: (p+46)h 1 150: (p+47)h 1 151: partition 2 (erase block type 1) bits per cell bits 0?3 = bits per cell in erase region bit 4 = reserved for ?internal ecc used? (1=yes, 0=no) bits 5?7 = reserve for future use partition 2 (erase block type 1) pagemode and synchronous mode capabilities as defined in table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3?7 = reserved for future use partition 2 (erase block type 2) bits per cell bits 0?3 = bits per cell in erase region bit 4 = reserved for ?internal ecc used? (1=yes, 0=no) bits 5?7 = reserve for future use partition 2 (erase block type 2) pagemode and synchronous mode capabilities as defined in table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3?7 = reserved for future use number of program or erase operations allowed in a partition bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations simultaneous program or erase operations allowed in other partitions while a partition in this region is in program mode bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations simultaneous program or erase operations allowed in other partitions while a partition in this region is in erase mode bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations types of erase block regions in this partition region. x = 0 = no erase blocking; the partition region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. symmetrica lly blocked par titions have one blocking region. partition size = (type 1 blocks)x(type 1 block sizes) + (type 2 blocks)x(type 2 block sizes) +?+ (type n blocks)x(type n block sizes)
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 100 251902-12 table 43: partition and erase block region information address 64 mbit ?b ?t ?b ?t ?b ?t 12d: --02 --02 --02 --02 --02 --02 12e: --01 --07 --01 --0f --01 --0f 12f: --00 --00 --00 --00 --00 --00 130: --11 --11 --11 --11 --11 --11 131: --00 --00 --00 --00 --00 --00 132: --00 --00 --00 --00 --00 --00 133: --02 --01 --02 --01 --02 --01 134: --03 --07 --03 --07 --03 --0f 135: --00 --00 --00 --00 --00 --00 136: --80 --00 --80 --00 --80 --00 137: --00 --02 --00 --02 --00 --02 138: --64 --64 --64 --64 --64 --64 139: --00 --00 --00 --00 --00 --00 13a: --02 --02 --02 --02 --02 --02 13b: --03 --03 --03 --03 --03 --03 13c: --06 --01 --06 --01 --0e --01 13d: --00 --00 --00 --00 --00 --00 13e: --00 --11 --00 --11 --00 --11 13f: --02 --00 --02 --00 --02 --00 140: --64 --00 --64 --00 --64 --00 141: --00 --02 --00 --02 --00 --02 142: --02 --06 --02 --06 --02 --0e 143: --03 --00 --03 --00 --03 --00 144: --07 --00 --0f --00 --0f --00 145: --00 --02 --00 --02 --00 --02 146: --11 --64 --11 --64 --11 --64 147: --00 --00 --00 --00 --00 --00 148: --00 --02 --00 --02 --00 --02 149: --01 --03 --01 --03 --01 --03 14a: --07 --03 --07 --03 --0f --03 14b: --00 --00 --00 --00 --00 --00 14c: --00 --80 --00 --80 --00 --80 14d: --02 --00 --02 --00 --02 --00 14e: --64 --64 --64 --64 --64 --64 14f: --00 --00 --00 --00 --00 --00 150: --02 --02 --02 --02 --02 --02 151: --03 --03 --03 --03 --03 --03 128 mbit 256 mbit
november 2007 datasheet 251902-12 101 numonyx? strataflash ? wireless memory (l18) appendix d additional information order/document number document/tool 251903 numonyx? strataflash ? wireless memory (l30) datasheet 290701 numonyx? wireless flash memory (w18) datasheet 290702 numonyx? wireless flash memory (w30) datasheet 290737 numonyx? strataflash ? synchronous memory (k3/k18) datasheet 251908 migration guide for 1.8 volt numonyx? wireless flash memory (w18/w30) to 1.8 volt numonyx? strataflash ? wireless memory (l18/l30), application note 753 251909 migration guide for 3 volt synchronous numonyx? strataflash ? memory (k3/k18) to 1.8 volt numonyx? strataflash ? wireless memory (l18/l30), application note 754 298161 numonyx? flash memory chip scale package user?s guide 297833 numonyx? flash data integrator (fdi) user?s guide 298136 numonyx? persistent storage manager user guide note: contact your local numonyx or distribution sales office or visit the numonyx world wide web home page at http:// www.numonyx.com for technical documentation, tools, and the most current information on numonyx? strataflash ? memory.
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 102 251902-12 appendix e ordering information t o order samples, obtain datasheets or inquire about any stack combination, please contact your local numonyx representative. table 44: 38f type stacked components pf 38f 5070 m0 y 0 b 0 package designator product line designator product die/ density configuration nor flash product family voltage/nor flash ce# configuration parameter / mux configuration ballout identifier device details pf = scsp, rohs rd = scsp, leaded stacked nor flash + ram char 1 = flash die #1 char 2 = flash die #2 char 3 = ram die #1 char 4 = ram die #2 (see ta b l e 4 6 , ?38f / 48f density decoder? on page 103 for details) first character applies to flash die #1 second character applies to flash die #2 (see ta b l e 4 7 , ?nor flash family decoder? on page 104 for details) v = 1.8 v core and i/o; separate chip enable per die (see ta b l e 4 8 , ?voltage / nor flash ce# configurati on decoder? on page 104 for details) 0 = no parameter blocks; non- mux i/o interface (see table 49, ?paramete r / mux configurati on decoder? on page 104 for details) b = x16d ballout (see ta b l e 5 0, ?ballout decoder ? on page 10 5 for details) 0 = original released version of this product
november 2007 datasheet 251902-12 103 numonyx? strataflash ? wireless memory (l18) table 45: 48f type stacked components pc 48f 4400 p0 v b 0 0 package designator product line designator product die/ density configuration nor flash product family voltage/no r flash ce# configuration parameter / mux configuration ballout identifier device details pc = easy bga, rohs rc = easy bga, leaded js = tsop, rohs te = tsop, leaded pf = scsp, rohs rd = scsp, leaded stacked nor flash only char 1 = flash die #1 char 2 = flash die #2 char 3 = flash die #3 char 4 = flash die #4 (see table 46, ?38f / 48f density decoder? on page 103 for details) first character applies to flash dies #1 and #2 second character applies to flash dies #3 and #4 (see ta b l e 4 7 , ?nor flash family decoder? on page 104 for details) v = 1.8 v core and 3 v i/o; virtual chip enable (see table 48, ?voltage / nor flash ce# configurati on decoder? on page 104 for details) b = bottom parameter; non-mux i/o interface (see table 49, ?paramete r / mux configurati on decoder? on page 104 for details) 0 = discrete ballout (see ta b l e 5 0, ?ballout decoder ? on page 10 5 for details) 0 = original released version of this product table 46: 38f / 48f density decoder code flash density ram density 0 no die no die 1 32-mbit 4-mbit 2 64-mbit 8-mbit 3 128-mbit 16-mbit 4 256-mbit 32-mbit 5 512-mbit 64-mbit 6 1-gbit 128-mbit 7 2-gbit 256-mbit 8 4-gbit 512-mbit 98-gbit 1-gbit a 16-gbit 2-gbit b 32-gbit 4-gbit c 64-gbit 8-gbit d 128-gbit 16-gbit e 256-gbit 32-gbit f 512-gbit 64-gbit
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 104 251902-12 table 47: nor flash family decoder code family marketing name c c3 numonyx advanced+ boot block flash memory j j3v.d numonyx embedded flash memory l l18 / l30 numonyx? strataflash? wireless memory m m18 numonyx? strataflash? cellular memory p p30 / p33 numonyx? stratafalsh? embedded memory w w18 / w30 numonyx? wireless flash memory 0(zero) - no die table 48: voltage / nor flash ce# configuration decoder code i/o voltage (volt) core voltage (volt) ce# configuration z 3.0 1.8 seperate chip enable per die y 1.8 1.8 seperate chip enable per die x 3.0 3.0 seperate chip enable per die v 3.0 1.8 virtual chip enable u 1.8 1.8 virtual chip enable t 3.0 3.0 virtual chip enable r3.0 1.8 virtual address q1.8 1.8 virtual address p3.0 3.0 virtual address table 49: parameter / mux configuration decoder (sheet 1 of 2) code, mux identificati on number of flash die bus width flash die 1 flash die 2 flash die 3 flash die 4 0 = non mux 1 = ad mux 1 2= aad mux 3 =full" ad mux 2 any na notation used for stacks that contain no parameter blocks b = non mux c = ad mux f = "full" ad mux 1 x16 bottom - - - 2 bottom top - - 3 bottom bottom top - 4 bottom top bottom top 2 x32 bottom bottom - - 4 bottom bottom top top
november 2007 datasheet 251902-12 105 numonyx? strataflash ? wireless memory (l18) t = non mux u = ad mux w = "full" ad mux 1 x16 to p - - - 2 top bottom - - 3 top top bottom - 4 top bottom top bottom 2 x32 to p to p - - 4 top top bottom bottom 1. only flash is muxed and ram is non-muxed 2. both flash and ram are ad-muxed table 50: ballout decoder code ballout definition 0 (zero) sdiscrete ballout (easay bga and tsop) b x16d ballout, 105 ball (x16 nor + nand + dram share bus) c x16c ballout, 107 ball (x16 nor + nand + psram share bus) q quad/+ ballout, 88 ball (x16 nor + psram share bus) u x32sh ballout, 106 ball (x32 nor only share bus) v x16sb ballout, 165 ball (x16 nor / nand + x16 dram split bus w x48d ballout, 165 ball (x16/x32 nor + nand + dram split bus table 49: parameter / mux configuration decoder (sheet 2 of 2) code, mux identificati on number of flash die bus width flash die 1 flash die 2 flash die 3 flash die 4
numonyx? strataflash ? wireless memory (l18) datasheet november 2007 106 251902-12

▲Up To Search▲

Price & Availability of 28F128L18

	To Download 28F128L18 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .